Dimitrios Velenis

According to our database, Dimitrios Velenis authored at least 39 papers between 2001 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Low-loss, multi-reticle stitched SiN waveguides for 300mm wafer-level optical interconnects.

Pengfei Xu, Chiara Marchese, Guy Lepage, Negin Golshani, Ruben Van Eenaeme, Andrea Mingardi, Joost Van Ongeval, Rafal Magdziak, Luc Halipre, Darko Trivkovic, Peter Verheyen, Maumita Chakrabarti, Dimitrios Velenis, Andy Miller, Filippo Ferraro, Yoojin Ban, Joris Van Campenhout

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024

Collective die-to-wafer bonding enabling low-loss evanescent coupling for optically interconnected System-on-Wafer.

Pengfei Xu, Junwen He, Koen Kennes, Anton Dvoretskii, Arnita Podpod, Guy Lepage, Negin Golshani, Rafal Magdziak, Swetanshu Bipul, Dieter Bode, Peter Verheyen, Maumita Chakrabarti, Dimitrios Velenis, Andy Miller, Yoojin Ban, Filippo Ferraro, Joris Van Campenhout

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024

32×100 GHz WDM filter based on ultra-compact silicon rings with a high thermal tuning efficiency of 5.85 mW/π.

Qingzhong Deng, Ahmed H. El-Saeed, Alaa Elshazly, Guy Lepage, Chiara Marchese, Hakim Kobbi, Rafal Magdziak, Jeroen De Coster, Neha Singh, Marko Ersek Filipcic, Kristof Croes, Dimitrios Velenis, Maumita Chakrabarti, Peter De Heyn, Peter Verheyen, Philippe Absil, Filippo Ferraro, Yoojin Ban, Joris Van Campenhout

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2024

2023

Highly Optimized O-band Si Ring Modulators for Low-Power Hybrid CMOS-SiPho Transceivers.

Yoojin Ban, Minkyu Kim, Peter De Heyn, Davide Guermandi, Filippo Ferraro, Natarajan Rajasekaran, Peter Verheyen, Pieter Bex, Junwen He, Hakim Kobbi, Jeroen De Coster, Rafal Magdziak, Dieter Bode, Sebastien Lardenois, Nicolas Pantano, Dimitrios Velenis, Joris Van Campenhout

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023

2022

84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor.

Hesheng Lin, Dimitrios Velenis, Philip Nolmans, Xiao Sun, Francky Catthoor, Rudy Lauwereins, Geert Van der Plas, Eric Beyne

IEEE Trans. Very Large Scale Integr. Syst., 2022

Efficient Backside Power Delivery for High-Performance Computing Systems.

Hesheng Lin, Geert Van der Plas, Xiao Sun, Dimitrios Velenis, Francky Catthoor, Rudy Lauwereins, Eric Beyne

IEEE Trans. Very Large Scale Integr. Syst., 2022

(Why do we need) Wireless Heterogeneous Integration (anyway?).

Michaël Peeters, S. Sinha, Xiao Sun, Claude Desset, Giuseppe Gramegna, John Slabbekoorn, Pieter Bex, N. Pinho, Tomas Webers, Dimitrios Velenis, A. Miller, Nadine Collaert, Geert Van der Plas, Eric Beyne, M. Huynen, R. Broucke

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021

110GHz Through-Silicon Via's Integrated in Silicon Photonics Interposers for Next-Generation Optical Modules.

Kenichi Miyaguchi, Yoojin Ban, Nicolas Pantano, Xiao Sun, Philippe Absil, Lieve Bogaerts, Peter Verheyen, Dimitrios Velenis, Marianna Pantouvaki, Joris Van Campenhout

Proceedings of the European Conference on Optical Communication, 2021

2019

Fabrication Cost Analysis for Contactless 3-D ICs.

Ioannis A. Papistas, Vasilis F. Pavlidis, Dimitrios Velenis

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Study of the Mechanical Stress Impact on Silicide Contact Resistance by 4-Point Bending.

Yefan Liu, Hao Yu, Gaspard Hiblot, Anastasiia Kruv, Marc Schaekers, Naoto Horiguchi, Dimitrios Velenis, Ingrid De Wolf

Proceedings of the IEEE International Reliability Physics Symposium, 2019

Process Complexity and Cost Considerations of Multi-Layer Die Stacks.

Dimitrios Velenis, Joeri De Vos, Soon-Wook Kim, Jaber Derakhshandeh, Pieter Bex, Giovanni Capuz, Samuel Suhard, Kenneth June Rebibis, Stefaan Van Huylenbroeck, Erik Jan Marinissen, Alain Phommahaxay, Andy Miller, Gerald Beyer, Geert Van der Plas, Eric Beyne

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2015

Active-lite interposer for 2.5 & 3D integration.

Geert Hellings, Mirko Scholz, Mikael Detalle, Dimitrios Velenis, Muriel de Potter de ten Broeck, C. Roda Neve, Y. Li, Stefaan Van Huylenbroeck, Shih-Hung Chen, Erik Jan Marinissen, Antonio La Manna, Geert Van der Plas, Dimitri Linten, Eric Beyne, Aaron Thean

Proceedings of the Symposium on VLSI Circuits, 2015

Processing active devices on Si interposer and impact on cost.

Dimitrios Velenis, Mikael Detalle, Geert Hellings, Mirko Scholz, Erik Jan Marinissen, Geert Van der Plas, Antonio La Manna, Andy Miller, Dimitri Linten, Eric Beyne

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2013

Si interposer build-up options and impact on 3D system cost.

Dimitrios Velenis, Mikael Detalle, Erik Jan Marinissen, Eric Beyne

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique.

Michele Stucchi, Dimitrios Velenis, Guruprasad Katti

IEEE Trans. Instrum. Meas., 2012

2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.

Geert Van der Plas, Paresh Limaye, Igor Loi, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Antonio Pullini, Federico Angiolini, Luca Benini, Wim Dehaene, Youssef Travaly, Eric Beyne, Paul Marchal

IEEE J. Solid State Circuits, 2011

Development of cost-effective biocompatible packaging for microelectronic devices.

Karen Qian, Karl Malachowski, Paolo Fiorini, Dimitrios Velenis, Maaike Op de Beeck, Chris Van Hoof

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

3D stacking using ultra thin dies.

Antonio La Manna, Dimitrios Velenis, Thibault Buisson, Mikael Detalle, Kenneth J. Rebibis, Wenqi Zhang, Eric Beyne

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

Design issues and considerations for low-cost 3D TSV IC technology.

Geert Van der Plas, Paresh Limaye, Abdelkarim Mercha, Herman Oprins, Cristina Torregiani, Steven Thijs, Dimitri Linten, Michele Stucchi, Guruprasad Katti, Dimitrios Velenis, Domae Shinichi, Vladimir Cherman, Bart Vandevelde, Veerle Simons, Ingrid De Wolf, Riet Labie, Dan Perry, Stephane Bronckers, Nikolaos Minas, Miro Cupac, Wouter Ruythooren, Jan Van Olmen, Alain Phommahaxay, Muriel de Potter de ten Broeck, Ann Opdebeeck, Michal Rakowski, Bart De Wachter, Morin Dehan, Marc Nelis, Rahul Agarwal, Wim Dehaene, Youssef Travaly, Pol Marchal, Eric Beyne

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

3D integration: Circuit design, test, and reliability challenges.

Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking.

Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis

Proceedings of the 15th European Test Symposium, 2010

Cost effectiveness of 3D integration options.

Dimitrios Velenis, Erik Jan Marinissen, Eric Beyne

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Effects of Parameter Variations on Timing Characteristics of Clocked Registers.

William R. Roberts, Dimitrios Velenis

J. Circuits Syst. Comput., 2009

Impact of 3D design choices on manufacturing cost.

Dimitrios Velenis, Michele Stucchi, Erik Jan Marinissen, Bart Swinnen, Eric Beyne

Proceedings of the IEEE International Conference on 3D System Integration, 2009

2007

Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees.

Boyan Semerdjiev, Dimitrios Velenis

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees.

Boyan Semerdjiev, Dimitrios Velenis

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks.

Itisha Chanodia, Dimitrios Velenis

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Power supply variation effects on timing characteristics of clocked registers.

William R. Roberts, Dimitrios Velenis

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Effects of crosstalk noise on H-tree clock distribution networks.

Itisha Chanodia, Dimitrios Velenis

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Effects of process and environmental variations on timing characteristics of clocked registers.

William R. Roberts, Dimitrios Velenis

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005

Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers.

William R. Roberts, Dimitrios Velenis

Proceedings of the Integrated Circuit and System Design, 2005

2004

Clock tree layout design for reduced delay uncertainty.

Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Buffer Sizing for Crosstalk Induced Delay Uncertainty.

Dimitrios Velenis, Eby G. Friedman

Proceedings of the Integrated Circuit and System Design, 2004

Buffer sizing for delay uncertainty induced by process variations.

Dimitrios Velenis, Ramyashree Sundaresha, Eby G. Friedman

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003

Reduced Delay Uncertainty in High Performance Clock Distribution Networks.

Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman

Proceedings of the 2003 Design, 2003

2002

Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling.

Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman

J. Circuits Syst. Comput., 2002

SaTPEP: A TCP Performance Enhancing Proxy for Satellite Links.

Dimitrios Velenis, Dimitrios Kalogeras, Basil S. Maglaris

Proceedings of the NETWORKING 2002, 2002

2001

A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.

Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Demonstration of speed enhancements on an industrial circuit through application of non-zero clock skew scheduling.

Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, Victor Adler, Franklin Baez, Eby G. Friedman

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001