Dimitrios Stamoulis
Orcid: 0000-0003-1682-9350
According to our database1,
Dimitrios Stamoulis
authored at least 29 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
CoRR, 2024
CoRR, 2024
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024
2023
2022
AntiDoteX: Attention-Based Dynamic Optimization for Neural Network Runtime Efficiency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
2021
Proceedings of the Second Teaching Machine Learning and Artificial Intelligence Workshop, 2021
2020
Single-Path Mobile AutoML: Efficient ConvNet Design and NAS Hyperparameter Optimization.
IEEE J. Sel. Top. Signal Process., 2020
Third ArchEdge Workshop: Exploring the Design Space of Efficient Deep Neural Networks.
CoRR, 2020
Towards Latency-aware DNN Optimization with GPU Runtime Analysis and Tail Effect Elimination.
CoRR, 2020
Proceedings of the 5th IEEE/ACM Symposium on Edge Computing, 2020
2019
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2019
2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
CoRR, 2017
Enhancing precipitation models by capturing multivariate and multiscale climate dynamics.
Proceedings of the 3rd International Workshop on Cyber-Physical Systems for Smart Water Networks, 2017
Proceedings of The 9th Asian Conference on Machine Learning, 2017
2016
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014