Dimitrios Stamoulis

Orcid: 0000-0003-1682-9350

According to our database1, Dimitrios Stamoulis authored at least 29 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
LLM-dCache: Improving Tool-Augmented LLMs with GPT-Driven Localized Data Caching.
CoRR, 2024

Unlearning Climate Misinformation in Large Language Models.
CoRR, 2024

Evaluating Zero-Shot GPT-4V Performance on 3D Visual Question Answering Benchmarks.
CoRR, 2024

An LLM-Tool Compiler for Fused Parallel Function Calling.
CoRR, 2024

Evaluating Tool-Augmented Agents in Remote Sensing Platforms.
CoRR, 2024

GeckOpt: LLM System Efficiency via Intent-Based Tool Selection.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

GeoLLM-Engine: A Realistic Environment for Building Geospatial Copilots.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2024

2023
Stable Diffusion For Aerial Object Detection.
CoRR, 2023

2022
AntiDoteX: Attention-Based Dynamic Optimization for Neural Network Runtime Efficiency.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2021
Putting the "Machine" Back in Machine Learning for Engineering Students.
Proceedings of the Second Teaching Machine Learning and Artificial Intelligence Workshop, 2021

2020
Single-Path Mobile AutoML: Efficient ConvNet Design and NAS Hyperparameter Optimization.
IEEE J. Sel. Top. Signal Process., 2020

Third ArchEdge Workshop: Exploring the Design Space of Efficient Deep Neural Networks.
CoRR, 2020

Towards Latency-aware DNN Optimization with GPU Runtime Analysis and Tail Effect Elimination.
CoRR, 2020

Exploring the Design Space of Efficient Deep Neural Networks.
Proceedings of the 5th IEEE/ACM Symposium on Edge Computing, 2020

2019
Single-Path NAS: Device-Aware Efficient ConvNet Design.
CoRR, 2019

Single-Path NAS: Designing Hardware-Efficient ConvNets in Less Than 4 Hours.
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2019

2018
Profit: Priority and Power/Performance Optimization for Many-Core Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Designing adaptive neural networks for energy-constrained image classification.
Proceedings of the International Conference on Computer-Aided Design, 2018

Hardware-aware machine learning: modeling and optimization.
Proceedings of the International Conference on Computer-Aided Design, 2018

HyperPower: Power- and memory-constrained hyper-parameter optimization for neural networks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
NeuralPower: Predict and Deploy Energy-Efficient Convolutional Neural Networks.
CoRR, 2017

Enhancing precipitation models by capturing multivariate and multiscale climate dynamics.
Proceedings of the 3rd International Workshop on Cyber-Physical Systems for Smart Water Networks, 2017

\emphNeuralPower: Predict and Deploy Energy-Efficient Convolutional Neural Networks.
Proceedings of The 9th Asian Conference on Machine Learning, 2017

2016
Can We Guarantee Performance Requirements under Workload and Process Variations?
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Exploring aging deceleration in FinFET-based multi-core systems.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Linear regression techniques for efficient analysis of transistor variability.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014


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