Dimitrios Soudris

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PetaOps/W edge-AI $\mu$ Processors: Myth or reality?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Profile-Driven Banded Smith-Waterman acceleration for Short Read Alignment.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

Darly: Deep Reinforcement Learning for QoS-aware scheduling under resource heterogeneity Optimizing serverless video analytics.

[BibT_eX]

[DOI]

Dimitrios Giagkos

Proceedings of the 16th IEEE International Conference on Cloud Computing, 2023

IRIS: Interference and Resource Aware Predictive Orchestration for ML Inference Serving.

[BibT_eX]

[DOI]

Aggelos Ferikoglou

Panos Chrysomeris

Manolis Katsaragakis

Proceedings of the 16th IEEE International Conference on Cloud Computing, 2023

PRAETORIAN: A Framework for the Protection of Critical Infrastructures from advanced Combined Cyber and Physical Threats.

[BibT_eX]

[DOI]

Antonios Karteris

Juan Jose Hernandez-Montesinos

Eva María Muñoz Navarro

Proceedings of the 18th International Conference on Availability, Reliability and Security, 2023

2022

EXA2PRO: A Framework for High Development Productivity on Heterogeneous Computing Systems.

[BibT_eX]

[DOI]

Athanasios I. Papadopoulos

Dionysios D. Kehagias

IEEE Trans. Parallel Distributed Syst., 2022

Repurposing GPU Microarchitectures with Light-Weight Out-Of-Order Execution.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2022

Enabling Large Scale Simulations for Particle Accelerators.

[BibT_eX]

[DOI]

Helga Timko

Panagiotis Tsapatsaris

IEEE Trans. Parallel Distributed Syst., 2022

GANDAFL: Dataflow Acceleration for Short Read Alignment on NGS Data.

[BibT_eX]

[DOI]

Georgi Gaydadjiev

IEEE Trans. Computers, 2022

Decision support for GPU acceleration by predicting energy savings and programming effort.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2022

HLF-Kubed: Blockchain-Based Resource Monitoring for Edge Clusters.

[BibT_eX]

[DOI]

Theodora A. Varvarigou

Ledger, 2022

Live demonstration of an SDN-reconfigurable, FPGA-based TxRx for an analog-IFoF/mmWave radio access network in an MNO's infrastructure.

[BibT_eX]

[DOI]

JOCN, 2022

Translating quality-driven code change selection to an instance of multiple-criteria decision making.

[BibT_eX]

[DOI]

Miltiadis G. Siavvas

Dionysios D. Kehagias

Inf. Softw. Technol., 2022

GPU accelerated blockchain over key-value database transactions.

[BibT_eX]

[DOI]

Antonios Litke

Theodora A. Varvarigou

Athanasios I. Papadopoulos

IET Blockchain, 2022

EDEN: A High-Performance, General-Purpose, NeuroML-Based Neural Simulator.

[BibT_eX]

[DOI]

Frontiers Neuroinformatics, 2022

CONVOLVE: Smart and seamless design of smart edge processors.

[BibT_eX]

[DOI]

CoRR, 2022

Approximate computing, skeleton programming and run-time scheduling in an algorithm for process design and controllability in distributed and heterogeneous infrastructures.

[BibT_eX]

[DOI]

Nikos Vasilas

Comput. Chem. Eng., 2022

Systematic Embedded Development and Implementation Techniques on Intel Myriad VPUs.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Combining Fault Tolerance Techniques and COTS SoC Accelerators for Payload Processing in Space.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Towards Employing FPGA and ASIP Acceleration to Enable Onboard AI/ML in Space Applications.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

High Level Synthesis Acceleration of Change Detection in Multi-Temporal High Resolution Sentinel-2 Satellite Images.

[BibT_eX]

[DOI]

Dimitris Mylonakis

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

The Impact of Dynamic Storage Allocation on CPython Execution Time, Memory Footprint and Energy Consumption: An Empirical Study.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

LSTM Acceleration with FPGA and GPU Devices for Edge Computing Applications in B5G MEC.

[BibT_eX]

[DOI]

Andreas Kosmas Kakolyris

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

End-to-End Real-Time Service Provisioning over a SDN-controllable 60 GHz analog FiWi X-haul for 5G Hot-Spot Networks.

[BibT_eX]

[DOI]

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

Designing Application Analysis Tools for Cross-Device Energy Consumption Estimation.

[BibT_eX]

[DOI]

Nikolaos Maidonis

Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

MAx-DNN: Multi-Level Arithmetic Approximation for Energy-Efficient DNN Hardware Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022

Improving the performance of RISC-V softcores on FPGA by exploiting PVT variability and DVFS.

[BibT_eX]

[DOI]

Endri Taka

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Energy Consumption Evaluation of Optane DC Persistent Memory for Indexing Data Structures.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on High Performance Computing, 2022

EVOLVE: Towards Converging Big-Data, High-Performance and Cloud-Computing Worlds.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SDK4ED: One-click platform for Energy-aware, Maintainable and Dependable Applications.

[BibT_eX]

[DOI]

Miltiadis G. Siavvas

Dimitrios Tsoukalas

Erol Gelenbe

Dionisis D. Kehagias

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Memory Management Methodology for Application Data Structure Refinement and Placement on Heterogeneous DRAM/NVM Systems.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SGRM: Stackelberg Game-Based Resource Management for Edge Computing Systems.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Cross-Layer Approximation For Printed Machine Learning Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Towards making the most of NLP-based device mapping optimization for OpenCL kernels.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2022

Sequence Clock: A Dynamic Resource Orchestrator for Serverless Architectures.

[BibT_eX]

[DOI]

Ioannis Fakinos

Proceedings of the IEEE 15th International Conference on Cloud Computing, 2022

A Methodology for enhancing Emergency Situational Awareness through Social Media.

[BibT_eX]

[DOI]

Antonios Karteris

Georgios Tzanos

Konstantinos P. Demestichas

Juliette Pauline Philibert

Carlos López Gómez

Proceedings of the ARES 2022: The 17th International Conference on Availability, Reliability and Security, Vienna,Austria, August 23, 2022

2021

Benchmark dataset for preprint: "EDEN: A high-performance, general-purpose, NeuroML-based neural simulator".

[BibT_eX]

[DOI]

Sotirios Panagiotou

Charalampos Sidiropoulos

Mario Negrello

Dataset, September, 2021

Benchmark dataset for preprint: "EDEN: A high-performance, general-purpose, NeuroML-based neural simulator".

[BibT_eX]

[DOI]

Sotirios Panagiotou

Charalampos Sidiropoulos

Mario Negrello

Dataset, September, 2021

Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-nm FinFET FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2021

Rusty: Runtime Interference-Aware Predictive Monitoring for Modern Multi-Tenant Systems.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2021

Improving Power of DSP and CNN Hardware Accelerators Using Approximate Floating-point Multipliers.

[BibT_eX]

[DOI]

Theodora Paparouni

Evangelos Petrongonas

ACM Trans. Embed. Comput. Syst., 2021

Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC.

[BibT_eX]

[DOI]

Evangelos Petrongonas

ACM Trans. Embed. Comput. Syst., 2021

Utilizing cloud FPGAs towards the open neural network standard.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2021

A Flexible Tool for Estimating Applications Performance and Energy Consumption Through Static Analysis.

[BibT_eX]

[DOI]

SN Comput. Sci., 2021

Experience With Managing Technical Debt in Scientific Software Development Using the EXA2PRO Framework.

[BibT_eX]

[DOI]

Nikolaos Nikolaidis

Dimitrios Zisis

IEEE Access, 2021

Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks.

[BibT_eX]

[DOI]

Ruben Domingo

David Merodio Codinachs

Isabelle Conway

IEEE Access, 2021

FaaS and Curious: Performance Implications of Serverless Functions on Edge Computing Platforms.

[BibT_eX]

[DOI]

Evangelos Apostolakis

Aphrodite Tzomaka

Christos Papakostopoulos

Konstantinos Stavrakakis

Proceedings of the High Performance Computing - ISC High Performance Digital 2021 International Workshops, Frankfurt am Main, Germany, June 24, 2021

FADE: FaaS-inspired application decomposition and Energy-aware function placement on the Edge.

[BibT_eX]

[DOI]

Proceedings of the SCOPES '21: 24th International Workshop on Software and Compilers for Embedded Systems, Eindhoven, The Netherlands, November 1, 2021

Interference-Aware Workload Placement for Improving Latency Distribution of Converged HPC/Big Data Cloud Infrastructures.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

The Known Unknowns: Discovering Trade-Offs Between Heterogeneous Code Changes - Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

ApproxQAM: High-Order QAM Demodulation Circuits with Approximate Arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

FPGA Acceleration of Generative Adversarial Networks for Image Reconstruction.

[BibT_eX]

[DOI]

Konstantinos Anagnostopoulos

Proceedings of the 10th International Conference on Modern Circuits and Systems Technologies, 2021

Towards sharing one FPGA SoC for both low-level PHY and high-level AI/ML computing at the edge.

[BibT_eX]

[DOI]

Ioannis Stratakos

Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2021

A PVT-Aware Voltage Scaling Method for Energy Efficient FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

FPGA & VPU Co-Processing in Space Applications: Development and Testing with DSP/AI Benchmarks.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

Resource Aware GPU Scheduling in Kubernetes Infrastructure.

[BibT_eX]

[DOI]

Aggelos Ferikoglou

Proceedings of the 12th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and 10th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2021

FPGA Acceleration of Short Read Alignment.

[BibT_eX]

[DOI]

Proceedings of the HEART '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2021

Exploiting the Potential of Approximate Arithmetic in DSP & AI Hardware Accelerators.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

FPGA acceleration in EVOLVE's Converged Cloud-HPC Infrastructure.

[BibT_eX]

[DOI]

Jean-Thomas Acquaviva

Huy-Nam Nguyen

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Demonstration of FPGA-based A-IFoF/mmWave transceiver integration in mobile infrastructure for beyond 5G transport.

[BibT_eX]

[DOI]

Giannis Giannoulis

Ioanna Mesogiti

Eleni Theodoropoulou

George L. Lyberopoulos

Dimitrios Apostolopoulos

Proceedings of the European Conference on Optical Communication, 2021

ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUs.

[BibT_eX]

[DOI]

Evangelos Petrongonas

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Thermal Comfort Aware Online Energy Management Framework for a Smart Residential Building.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Performance Analysis and Auto-tuning for SPARK in-memory analytics.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

EVOLVE: HPC and cloud enhanced testbed for extracting value from large-scale diverse data.

[BibT_eX]

[DOI]

Antony Chazapis

Jean-Thomas Acquaviva

Proceedings of the CF '21: Computing Frontiers Conference, 2021

Covid4HPC: A Fast and Accurate Solution for Covid Detection in the Cloud Using X-Rays.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020

High-Performance Vision-Based Navigation on SoC FPGA for Spacecraft Proximity Operations.

[BibT_eX]

[DOI]

Xenophon Zabulis

IEEE Trans. Circuits Syst. Video Technol., 2020

Rapid Prototyping of Low-Complexity Orchestrator Targeting CyberPhysical Systems: The Smart-Thermostat Usecase.

[BibT_eX]

[DOI]

IEEE Trans. Control. Syst. Technol., 2020

Fast Operation Mode Selection for Highly Efficient IoT Edge Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Analog fiber-wireless downlink transmission of IFoF/mmWave over in-field deployed legacy PON infrastructure for 5G fronthauling.

[BibT_eX]

[DOI]

Dimitrios Apostolopoulos

Nikos Pleros

JOCN, 2020

Automated Physics-Derived Code Generation for Sensor Fusion and State Estimation.

[BibT_eX]

[DOI]

Orestis Kaparounakis

Phillip Stanley-Marbell

CoRR, 2020

Interference-Aware Orchestration in Kubernetes.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2020

Portable exploitation of parallel and heterogeneous HPC architectures in neural simulation using SkePU.

[BibT_eX]

[DOI]

Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020

Exploration of GPU sharing policies under GEMM workloads.

[BibT_eX]

[DOI]

Ioannis Oroutzoglou

Proceedings of the SCOPES '20: 23rd International Workshop on Software and Compilers for Embedded Systems, 2020

Technical Debt Management and Energy Consumption Evaluation in Implantable Medical Devices: The SDK4ED Approach.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Hardware Acceleration of Decision Tree Learning Algorithm.

[BibT_eX]

[DOI]

Asim Zoulkatni

Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

Fast Packet Classification using RISC-V and HyperSplit Acceleration on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Memory Footprint Optimization Techniques for Machine Learning Applications in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Combining Arithmetic Approximation Techniques for Improved CNN Circuit Design.

[BibT_eX]

[DOI]

George Chatzitsompanis

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

The SDK4ED Platform for Embedded Software Quality Improvement - Preliminary Overview.

[BibT_eX]

[DOI]

Miltiadis G. Siavvas

Dimitrios Tsoukalas

Marija Jankovic

Dionisis D. Kehagias

Proceedings of the Computational Science and Its Applications - ICCSA 2020, 2020

Automatic Generation of FPGA Kernels From Open Format CNN Models.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Resource-Aware MapReduce Runtime for Multi/Many-core Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

DDOT: Data Driven Online Tuning for energy efficient acceleration.

[BibT_eX]

[DOI]

Eleftherios-Iordanis Christoforidis

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Scale-out beam longitudinal dynamics simulations.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

A novel simulator for extended Hodgkin-Huxley neural networks.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Conference on Bioinformatics and Bioengineering, 2020

Exploiting the SoC FPGA Capabilities in the Control Architecture of a Quadruped Robot.

[BibT_eX]

[DOI]

Chrysostomos Karakasis

Konstantinos Machairas

Iosif S. Paraskevas

Evangelos Papadopoulos

Proceedings of the IEEE/ASME International Conference on Advanced Intelligent Mechatronics, 2020

2019

<i>Oops</i>: Optimizing Operation-mode Selection for IoT Edge Devices.

[BibT_eX]

[DOI]

ACM Trans. Internet Techn., 2019

A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

Single- and Multi-FPGA Acceleration of Dense Stereo Vision for Planetary Rovers.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures.

[BibT_eX]

[DOI]

Zois-Gerasimos Tasoulas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

In-the-Field Mitigation of Process Variability for Improved FPGA Performance.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point.

[BibT_eX]

[DOI]

Integr., 2019

Multinode implementation of an extended Hodgkin-Huxley simulator.

[BibT_eX]

[DOI]

Neurocomputing, 2019

Energy-efficient VLSI implementation of multipliers with double LSB operands.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2019

Rusty: Runtime System Predictability Leveraging LSTM Neural Networks.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

LOOG: Improving GPU Efficiency With Light-Weight Out-Of-Order Execution.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2019

Approximate Similarity Search with FAISS Framework Using FPGAs on the Cloud.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

FPGA Acceleration of Approximate KNN Indexing on High- Dimensional Vectors.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

A Synergy of a Closed-Loop DVFS Controller and CPU Hot-Plug For Run-Time Thermal Management in Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

Design of a Real-Time DSP Engine on RF-SoC FPGA for 5G Networks.

[BibT_eX]

[DOI]

Dimitrios Apostolopoulos

Proceedings of the Optical Network Design and Modeling, 2019

Hardware Acceleration on Gaussian Naive Bayes Machine Learning Algorithm.

[BibT_eX]

[DOI]

Georgios Tzanos

Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

TF2FPGA: A Framework for Projecting and Accelerating Tensorflow CNNs on FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Analysis of Performance Variation in 16nm FinFET FPGA Devices.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

Dataflow Acceleration of Smith-Waterman with Traceback for High Throughput Next Generation Sequencing.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Modular FPGA Acceleration of Data Analytics in Heterogenous Computing.

[BibT_eX]

[DOI]

Elias Koromilas

Francisco J. Ballesteros

Patricio Martínez

Ricardo Jiménez-Peris

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

DMRM: Distributed Market-Based Resource Management of Edge Computing Systems.

[BibT_eX]

[DOI]

Manolis Katsaragakis

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Cooperative Arithmetic-Aware Approximation Techniques for Energy-Efficient Multipliers.

[BibT_eX]

[DOI]

Konstantinos Asimakopoulos

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Hardware Acceleration of Image Registration Algorithm on FPGA-based Systems on Chip.

[BibT_eX]

[DOI]

Ioannis Stratakos

Dimitrios Gourounas

Theodore L. Economopoulos

George K. Matsopoulos

Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

GPU Implementation of Neural-Network Simulations Based on Adaptive-Exponential Models.

[BibT_eX]

[DOI]

Alexandros Neofytou

Proceedings of the 19th IEEE International Conference on Bioinformatics and Bioengineering, 2019

2018

High-Performance Embedded Computing in Space: Evaluation of Platforms for Vision-Based Navigation.

[BibT_eX]

[DOI]

Odysseas Papanikolaou

Xenophon Zabulis

Gianluca Furano

J. Aerosp. Inf. Syst., April, 2018

VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Runtime Slack Creation for Processor Performance Variability using System Scenarios.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Application-Arrival Rate Aware Distributed Run-Time Resource Management for Many-Core Computing Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2018

A Hierarchical Distributed Runtime Resource Management Scheme for NoC-Based Many-Cores.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2018

OpenCL-based Virtual Prototyping and Simulation of Many-Accelerator Architectures.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2018

Distributed Trade-Based Edge Device Management in Multi-Gateway IoT.

[BibT_eX]

[DOI]

ACM Trans. Cyber Phys. Syst., 2018

A Design Space Exploration Framework for Convolutional Neural Networks Implemented on Edge Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Walking through the Energy-Error Pareto Frontier of Approximate Multipliers.

[BibT_eX]

[DOI]

IEEE Micro, 2018

Decoupled MapReduce for Shared-Memory Multi-Core Architectures.

[BibT_eX]

[DOI]

Eleftherios-Iordanis Christoforidis

IEEE Comput. Archit. Lett., 2018

CF-TUNE: Collaborative Filtering Auto-Tuning for Energy Efficient Many-Core Processors.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2018

Interrelations between Software Quality Metrics, Performance and Energy Consumption in Embedded Applications.

[BibT_eX]

[DOI]

Georgios Digkas

Proceedings of the 21st International Workshop on Software and Compilers for Embedded Systems, 2018

EXA2PRO programming environment: architecture and applications.

[BibT_eX]

[DOI]

Athanasios I. Papadopoulos

Christoph W. Kessler

Dionysios D. Kehagias

Panos Seferlis

Sharatchandra Varma Bogaraju

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

The VINEYARD integrated framework for hardware accelerators in the cloud.

[BibT_eX]

[DOI]

Hans Vandierendonck

Dimitrios S. Nikolopoulos

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

BLonD++: performance analysis and optimizations for enabling complex, accurate and fast beam dynamics studies.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Real-Time Carrier Phase Recovery for 16-QAM Utilizing the Nonlinear Least Squares Algorithm.

[BibT_eX]

[DOI]

Vatistas Kostalampros

Proceedings of the Optical Fiber Communications Conference and Exposition, 2018

Fast Estimations of Failure Probability Over Long Time Spans.

[BibT_eX]

[DOI]

Michail Noltsis

Panayiotis Englezakis

Eleni Maragkoudaki

Chrysostomos Nicopoulos

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Efficient support vector machines implementation on Intel/Movidius Myriad 2.

[BibT_eX]

[DOI]

Nikolaos Karavalakis

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Acceleration of image classification with Caffe framework using FPGA.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

Carrier Phase Recovery of 64 GBd Optical 16-QAM Using Extensive Parallelization on an FPGA.

[BibT_eX]

[DOI]

Vatistas Kostalampros

Stefanos Dris

André Richter

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Novel Framework for the Seamless Integration of FPGA Accelerators with Big Data Analytics Frameworks in Heterogeneous Data Centers.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Conference on High Performance Computing & Simulation, 2018

Parity Based In-Place FFT Architecture for Continuous Flow Applications.

[BibT_eX]

[DOI]

Vasileios Kitsakis

Dionisios I. Reisis

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Parallel Robust Absolute Orientation on FPGA for Vision and Robotics.

[BibT_eX]

[DOI]

Nikolaos Dimou

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Framework Exploiting Process Variability to Improve Energy Efficiency in FPGA Applications.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Towards plug&play smart thermostats inspired by reinforcement learning.

[BibT_eX]

[DOI]

Proceedings of the Workshop on INTelligent Embedded Systems Architectures and Applications, 2018

The VINEYARD Framework for Heterogeneous Cloud Applications: The BrainFrame Case.

[BibT_eX]

[DOI]

Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018

Efficient winograd-based convolution kernel implementation on edge devices.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

Efficient Hardware Acceleration of Recommendation Engines: A Use Case on Collaborative Filtering.

[BibT_eX]

[DOI]

Konstantinos Katsantonis

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Seamless FPGA Deployment over Spark in Cloud Computing: A Use Case on Machine Learning Hardware Acceleration.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018

Evaluation Methodology and Reconfiguration Tests on the New European NG-MEDIUM FPGA.

[BibT_eX]

[DOI]

Ruben Domingo

Antonio Pastor

David Merodio Codinachs

Isabelle Conway

Proceedings of the 2018 NASA/ESA Conference on Adaptive Hardware and Systems, 2018

2017

An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2017

A Flexible, High-Performance FPGA Implementation of a Feed-Forward Equalizer for Optical Interconnects up to 112 Gb/s.

[BibT_eX]

[DOI]

Paraskevas Bakopoulos

J. Signal Process. Syst., 2017

An FPGA-based Integrated MapReduce Accelerator Platform.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2017

Optimizing Extended Hodgkin-Huxley Neuron Model Simulations for a Xeon/Xeon Phi Node.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2017

SoftRM: Self-Organized Fault-Tolerant Resource Management for Failure Detection and Recovery in NoC Based Many-Cores.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2017

On supporting rapid prototyping of embedded systems with reconfigurable architectures.

[BibT_eX]

[DOI]

Integr., 2017

A Flexible Decision-Making Mechanism Targeting Smart Thermostats.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2017

From Knights Corner to Landing: A Case Study Based on a Hodgkin-Huxley Neuron Simulator.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing, 2017

Network/system co-simulation for design space exploration of IoT applications.

[BibT_eX]

[DOI]

Zhuoran Zhao

Andreas Gerstlauer

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Hardware accelerators for financial applications in HDL and High Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Algorithmic and memory optimizations on multiple application mapping onto FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

SPynq: Acceleration of machine learning applications over Spark on Pynq.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructure.

[BibT_eX]

[DOI]

Ioannis Bakolas

Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

FabSpace 2.0: A platform for application and service development based on Earth Observation data.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Spark acceleration on FPGAs: A use case on machine learning in Pynq.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

Project HIPNOS: Case Study of High Performance Avionics for Active Debris Removal in Space.

[BibT_eX]

[DOI]

Xenophon Zabulis

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

FPGA acceleration of hyperspectral image processing for high-speed detection applications.

[BibT_eX]

[DOI]

Konstantinos Karantzalos

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

FabSpace 2.0: The open-innovation network for geodata-driven innovation.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Geoscience and Remote Sensing Symposium, 2017

Dataflow Acceleration of scikit-learn Gaussian Process Regression.

[BibT_eX]

[DOI]

Michail Doukas

Shalina Percy Delicia Figuli

Proceedings of the 8th Workshop and 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms, 2017

High-Performance Hardware Accelerators for Solving Ordinary Differential Equations.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

VineTalk: Simplifying software access and sharing of FPGAs in datacenters.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

FPGA acceleration of spark applications in a Pynq cluster.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

HARPA: Tackling physically induced performance variability.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Application performance improvement by exploiting process variability on FPGA devices.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

FabSpaces at ImageCLEF 2017 - Population Estimation (remote) Task.

[BibT_eX]

[DOI]

Proceedings of the Working Notes of CLEF 2017, 2017

Parameter Sensitivity in Virtual FPGA Architectures.

[BibT_eX]

[DOI]

Peter Figuli

Weiqiao Ding

Jürgen Becker

Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016

Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Framework for Interconnection-Aware Domain-Specific Many-Accelerator Synthesis.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2016

An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2016

Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations.

[BibT_eX]

[DOI]

Maria-Iro Baka

ACM Trans. Embed. Comput. Syst., 2016

HW/SW Codesign and FPGA Acceleration of Visual Odometry Algorithms for Rover Navigation on Mars.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2016

A Customizable Framework for Application Implementation onto 3-D FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Systematic Methodology for Optimization of Applications Utilizing Concurrent Data Structures.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

Effective Learning and Filtering of Faulty Heart-Beats for Advanced ECG Arrhythmia Detection using MIT-BIH Database.

[BibT_eX]

[DOI]

Dimitra Azariadi

EAI Endorsed Trans. Pervasive Health Technol., 2016

Customization methodology for implementation of streaming aggregation in embedded systems.

[BibT_eX]

[DOI]

J. Syst. Archit., 2016

Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2016

ANT3D: Simultaneous Partitioning and Placement for 3-D FPGAs based on Ant Colony Optimization.

[BibT_eX]

[DOI]

Panayiotis Danassis

Georgios Chatzikonstantis

IEEE Embed. Syst. Lett., 2016

BrainFrame: A node-level heterogeneous accelerator platform for neuron simulations.

[BibT_eX]

[DOI]

Georgios Smaragdos

CoRR, 2016

A Survey on FEC Codes for 100 G and Beyond Optical Networks.

[BibT_eX]

[DOI]

IEEE Commun. Surv. Tutorials, 2016

Computation offloading and resource allocation for low-power IoT edge devices.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE World Forum on Internet of Things, 2016

Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend.

[BibT_eX]

[DOI]

Georgios Zervakis

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

Performance and energy evaluation of spark applications on low-power SoCs.

[BibT_eX]

[DOI]

Ioannis Stamelos

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A framework for exploring alternative fault-tolerant schemes targeting 3-D reconfigurable architectures.

[BibT_eX]

[DOI]

Ioannis Savidis

Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

A Co-Design Approach For Rapid Prototyping Of Image Processing On SoC FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 20th Pan-Hellenic Conference on Informatics, 2016

Energy profile analysis of Zynq-7000 programmable SoC for embedded medical processing: Study on ECG arrhythmia detection.

[BibT_eX]

[DOI]

Konstantinos Railis

Georgios Chatzikonstantis

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Performance analysis of accelerated biophysically-meaningful neuron simulations.

[BibT_eX]

[DOI]

Georgios Smaragdos

Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

Accuracy of Quasi-Monte Carlo technique in failure probability estimations.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IC Design and Technology, 2016

A 56 Gbaud reconfigurable FPGA feed-forward equalizer for optical datacenter networks with flexible baudrate- and modulation-format.

[BibT_eX]

[DOI]

Christos Spatharakis

Giannis Kanakis

Nikolaos Iliadis

Paraskevas Bakopoulos

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Agora: Agent and market-based resource management for many-core systems.

[BibT_eX]

[DOI]

Themistoklis Melissaris

Andreas-Lazaros Georgiadis

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Deploying and monitoring hadoop MapReduce analytics on single-chip cloud computer.

[BibT_eX]

[DOI]

Proceedings of the 7th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 5th Workshop on Design Tools and Architectures For Multicore Embedded Computing Platforms, 2016

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

A survey on reconfigurable accelerators for cloud computing.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016

Runtime interval optimization and dependable performance for application-level checkpointing.

[BibT_eX]

[DOI]

Apostolos Kokolis

Alexandros Mavrogiannis

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Distributed QoS management for internet of things under resource constraints.

[BibT_eX]

[DOI]

Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

First impressions from detailed brain model simulations on a Xeon/Xeon-Phi node.

[BibT_eX]

[DOI]

Dimitrios S. Nikolopoulos

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

Runtime management of adaptive MPSoCs for graceful degradation.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Compilers, 2016

The VINEYARD Approach: Versatile, Integrated, Accelerator-Based, Heterogeneous Data Centres.

[BibT_eX]

[DOI]

Ricardo Jiménez-Peris

Alexandre Almeida

Proceedings of the Applied Reconfigurable Computing - 12th International Symposium, 2016

2015

Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2015

GENESIS: Parallel Application Placement onto Reconfigurable Architectures (Invited for the Special Issue on Runtime Management).

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2015

A MapReduce scratchpad memory for multi-core cloud computing applications.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

Using Chaos Theory based workload analysis to perform Dynamic Frequency Scaling on MPSoCs.

[BibT_eX]

[DOI]

J. Syst. Archit., 2015

Performance and power consumption evaluation of concurrent queue implementations in embedded systems.

[BibT_eX]

[DOI]

Comput. Sci. Res. Dev., 2015

An Evolutionary Algorithm for Netlist Partitioning Targeting 3-D FPGAs.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2015

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2015

Tackling Performance Variability Due to RAS Mechanisms with PID-Controlled DVFS.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2015

Mitigating Memory-Induced Dark Silicon in Many-Accelerator Architectures.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2015

An Energy Efficient Message Passing Synchronization Algorithm for Concurrent Data Structures in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

AEGLE: A big bio-data analytics framework for integrated health-care services.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

HARPA: Solutions for dependable performance under physically induced performance variability.

[BibT_eX]

[DOI]

Chrysostomos Nicopoulos

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Platform-aware dynamic data type refinement methodology for radix tree Data Structures.

[BibT_eX]

[DOI]

Thomas Papastergiou

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Hybrid approximate multiplier architectures for improved power-accuracy trade-offs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Many-core CPUs can deliver scalable performance to stochastic simulations of large-scale biochemical reaction networks.

[BibT_eX]

[DOI]

Elias Kouskoumvekakis

Elias S. Manolakos

Proceedings of the 2015 International Conference on High Performance Computing & Simulation, 2015

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

High-Level-Synthesis extensions for scalable Single-Chip Many-Accelerators on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Job-Arrival Aware Distributed Run-Time Resource Management on Intel SCC Manycore Platform.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

Advancing Integrated and Personalized Healthcare Services, the AEGLE Approach.

[BibT_eX]

[DOI]

Andreas Raptopoulos

Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring.

[BibT_eX]

[DOI]

Leonidas Lymperopoulos

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools.

[BibT_eX]

[DOI]

Shalina Percy Delicia

Jürgen Becker

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Reconfigurable Computing for Analytics Acceleration of Big Bio-Data: The AEGLE Approach.

[BibT_eX]

[DOI]

Andreas Raptopoulos

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

SPARTAN/SEXTANT/COMPASS: Advancing Space Rover Vision via Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

Dynamic Memory Management in Vivado-HLS for Scalable Many-Accelerator Architectures.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014

A Framework for Supporting Adaptive Fault-Tolerant Solutions.

[BibT_eX]

[DOI]

Michael Hübner

ACM Trans. Embed. Comput. Syst., 2014

Plug&Chip: A Framework for Supporting Rapid Prototyping of 3D Hybrid Virtual SoCs.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2014

A framework for rapid evaluation of heterogeneous 3-D NoC architectures.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

A novel 3-D FPGA architecture targeting communication intensive applications.

[BibT_eX]

[DOI]

J. Syst. Archit., 2014

SPARTAN: Developing a Vision System for Future Autonomous Space Exploration Robots.

[BibT_eX]

[DOI]

Ioannis Kostavelis

Lazaros Nalpantidis

Evangelos Boukas

Antonios Gasteratos

J. Field Robotics, 2014

Network Function Virtualization based on FPGAs: A Framework for all-Programmable network devices.

[BibT_eX]

[DOI]

CoRR, 2014

Optimal mapping of inferior olive neuron simulations on the Single-Chip Cloud Computer.

[BibT_eX]

[DOI]

Giorgos Chatzikonstantis

Andreas Pantelopoulos

Chris I. De Zeeuw

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Evaluation of message passing synchronization algorithms in embedded systems.

[BibT_eX]

[DOI]

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

A HW/SW framework emulating wearable devices for remote wound monitoring and management.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014

SWAN-iCare project: Towards smart wearable and autonomous negative pressure device for wound monitoring and therapy.

[BibT_eX]

[DOI]

Leonidas Lymberopoulos

Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014

Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014

A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCs.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on System-on-Chip, 2014

A Low-Latency Algorithm and FPGA Design for the Min-Search of LDPC Decoders.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

A Framework for Customizing Virtual 3-D Reconfigurable Platforms at Run-Time.

[BibT_eX]

[DOI]

Michael Hübner

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

A Framework for Mapping Dynamic Virtual Kernels onto Heterogeneous Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

Linear regression techniques for efficient analysis of transistor variability.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A MapReduce framework implementation for Network-on-Chip platforms.

[BibT_eX]

[DOI]

Konstantinos Gyftakis

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks.

[BibT_eX]

[DOI]

Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014

A configurable mapreduce accelerator for multi-core FPGAs (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Systematic Exploration of Power-Aware Scenarios for IEEE 802.11ac WLAN Systems.

[BibT_eX]

[DOI]

Iason Filippopoulos

Per Gunnar Kjeldsberg

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2013

JITPR: A framework for supporting fast application's implementation onto FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2013

Power-aware dynamic memory management on many-core platforms utilizing DVFS.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2013

A low-cost fault tolerant solution targeting commercial FPGA devices.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

On supporting rapid exploration of memory hierarchies onto FPGAs.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios.

[BibT_eX]

[DOI]

Int. J. Wirel. Inf. Networks, 2013

A Novel Prototyping and Evaluation Framework for NoC-Based MPSoC.

[BibT_eX]

[DOI]

Int. J. Adapt. Resilient Auton. Syst., 2013

SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapy.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

A Process-based Reconfigurable SystemC Module for simulation speedup.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013

Automatic implementation of low-complexity QC-LDPC encoders.

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A new design paradigm for floating point DSP applications based on ESL/HLS and FPGAs?

[BibT_eX]

[DOI]

Christoforos E. Economakos

Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2013

On Supporting Adaptive Fault Tolerant at Run-Time with Virtual FPGAs.

[BibT_eX]

[DOI]

Michael Hübner

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

A low-complexity implementation of QC-LDPC encoder in reconfigurable logic.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Distributed run-time resource management for malleable applications on many-core platforms.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

A Systematic Methodology for Reliability Improvements on SoC-Based Software Defined Radio Systems.

[BibT_eX]

[DOI]

VLSI Design, 2012

A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric.

[BibT_eX]

[DOI]

Vasilis F. Pavlidis

ACM Trans. Reconfigurable Technol. Syst., 2012

Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

High-level customization framework for application-specific NoC architectures.

[BibT_eX]

[DOI]

Iasonas Filippopoulos

Des. Autom. Embed. Syst., 2012

Adaptive dynamic memory allocators by estimating application workloads.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments.

[BibT_eX]

[DOI]

Dimitris Bekiaris

Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012

Run-Time Measurement of Harvested Energy for Autarkic Sensor Operation.

[BibT_eX]

[DOI]

Dimitris Bekiaris

Ioannis Kosmadakis

George I. Stassinopoulos

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

FPGA-based path-planning of high mobility rover for future planetary missions.

[BibT_eX]

[DOI]

G. Stamoulias

Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Parallel paradigms and run-time management techniques for many-core architectures: the 2PARMA approach.

[BibT_eX]

[DOI]

Proceedings of the 2012 Interconnection Network Architecture, 2012

Hardware implementation of stereo correspondence algorithm for the ExoMars mission.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A divide and conquer based distributed run-time mapping methodology for many-core platforms.

[BibT_eX]

[DOI]

Georgios Kathareios

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Performance Evaluation of Embedded Processor in MapReduce Cloud Computing Applications.

[BibT_eX]

[DOI]

Proceedings of the Cloud Computing - Third International Conference, 2012

Run-Time Dynamic Data Type Transformations.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

Efficient Memory Allocations on a Many-Core Accelerator.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012

A low-cost fault tolerant solution targeting to commercial FPGA devices.

[BibT_eX]

[DOI]

Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

SPARTAN project: On profiling computer vision algorithms for rover navigation.

[BibT_eX]

[DOI]

Proceedings of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, 2012

2011

High Performance and Area Efficient Flexible DSP Datapath Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

FILESPPA: Fast Instruction Level Embedded System Power and Performance Analyzer.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2011

A Tabu-Based Partitioning and Layer Assignment Algorithm for 3-D FPGAs.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2011

Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2011

On Supporting Rapid Thermal Analysis.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2011

Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Thermal optimization for micro-architectures through selective block replication.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

SPARTAN project: Efficient implementation of computer vision algorithms onto reconfigurable platform targeting to space applications.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Invited paper: Parallel programming and run-time resource management framework for many-core platforms: The 2PARMA approach.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Low-Power Reconfigurable Component Utilization in a High-Level Synthesis Flow.

[BibT_eX]

[DOI]

Dimitris Bekiaris

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

A Framework for Architecture-Level Exploration of 3-D FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

CAD tools for designing 3D integrated systems.

[BibT_eX]

[DOI]

Antonis Papanikolaou

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Design and experimentation with low-power morphable multipliers.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Configurable baseband digital transceiver for Gbps wireless 60 GHz communications.

[BibT_eX]

[DOI]

Panagiotis Galiatsatos

Athanasios Karachalios

Dionisios I. Reisis

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A Methodology and Tool Framework for Supporting Rapid Exploration of Memory Hierarchies in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A Framework for Architecture-Level Exploration of Communication Intensive Applications onto 3-D FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Runtime Tuning of Dynamic Memory Management For Mitigating Footprint-Fragmentation Variations.

[BibT_eX]

[DOI]

Ioannis S. Stamelakos

Proceedings of the ARCS 2011, 2011

Trading Fault-Masking with Performance Overhead for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2011, 2011

Quick_Hotspot: A Software Supported Methodology for Supporting Run-Time Thermal Analysis at MPSoC Designs.

[BibT_eX]

[DOI]

Proceedings of the ARCS 2011, 2011

2010

Software metadata: Systematic characterization of the memory behaviour of dynamic applications.

[BibT_eX]

[DOI]

J. Syst. Softw., 2010

A Novel Allocation Methodology for Partial and Dynamic Bitstream Generation for FPGA Architectures.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2010

A Methodology for Alleviating the Performance Degradation of TMR Solutions.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2010

An automatic framework for dynamic data structures optimization in C.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Custom multi-threaded Dynamic Memory Management for Multiprocessor System-on-Chip platforms.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching.

[BibT_eX]

[DOI]

Christos Skouroumounis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Towards Supporting Fault-Tolerance in FPGAs.

[BibT_eX]

[DOI]

Dionisios N. Pnevmatikatos

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures.

[BibT_eX]

[DOI]

Iasonas Filippopoulos

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

The MOSART Mapping Optimization for Multi-Core ARchiTectures.

[BibT_eX]

[DOI]

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Mapping Embedded Applications on MPSoCs: The MNEMEE Approach.

[BibT_eX]

[DOI]

Dimitrios Kritharidis

Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010

Mapping Embedded Applications on MPSoCs: The MNEMEE Approach.

[BibT_eX]

[DOI]

Dimitrios Kritharidis

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology.

[BibT_eX]

[DOI]

Christos Skouroumounis

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Multiple Vdd on 3D NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

NAROUTO: An open-source framework for supporting architecture-level exploration at heterogeneous FPGAS.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

BIT-width exploration over 3D architectures using high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Construction of dual mode components for reconfiguration aware high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

MNEMEE: a framework for memory management and optimization of static and dynamic data in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Compilers, 2010

Dynamic Frequency Scaling for MPSoCs based on Chaotic Workload Analysis.

[BibT_eX]

[DOI]

Georgios P. Pavlos

Proceedings of the ARCS '10, 2010

Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's.

[BibT_eX]

[DOI]

Proceedings of the ARCS '10, 2010

A Framework for Enabling Fault Tolerance in Reconfigurable Architectures.

[BibT_eX]

[DOI]

Dionisios N. Pnevmatikatos

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems.

[BibT_eX]

[DOI]

José Luis Risco-Martín

J. Syst. Softw., 2009

Designing a novel high-performance FPGA architecture for data intensive applications.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2009

Direct memory access usage optimization in network applications for reduced memory latency and energy consumption.

[BibT_eX]

[DOI]

J. Embed. Comput., 2009

A system-level design methodology for application-specific networks-on-chip.

[BibT_eX]

[DOI]

J. Embed. Comput., 2009

Design and implementation of a DDS-based multi-carrier GMSK modulator.

[BibT_eX]

[DOI]

John N. Lygouras

John N. Sahalos

Int. J. Commun. Syst., 2009

High-level estimation methodology for designing the instruction cache memory of programmable embedded platforms.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms.

[BibT_eX]

[DOI]

Liesbet Van der Perre

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Dynamic Data Type Optimization and Memory Assignment Methodologies.

[BibT_eX]

[DOI]

Fragkiskos Ieromnimon

Nikolaos S. Voros

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Application-Specific Temperature Reduction Systematic Methodology for 2D and 3D Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Digital Signal Processing, 2009

Node resource management for DSP applications on 3D Network-on-Chip architecture.

[BibT_eX]

[DOI]

Ioannis Vourkas

Proceedings of the 16th International Conference on Digital Signal Processing, 2009

Compilation Technique for Loop Overhead Minimization.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAs.

[BibT_eX]

[DOI]

Vasilis F. Pavlidis

Proceedings of the Design, Automation and Test in Europe, 2009

2008

A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Exploration methodology of dynamic data structures in multimedia and network applications for embedded platforms.

[BibT_eX]

[DOI]

J. Syst. Archit., 2008

Designing a General-Purpose Interconnection Architecture for Field Programmable Gate Arrays.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

A Power-Aware Placement and Routing Algorithm Targeting 3D FPGAs.

[BibT_eX]

[DOI]

J. Low Power Electron., 2008

Architecture-Level Exploration of Alternative Interconnection Schemes Targeting 3D FPGAs: A Software-Supported Methodology.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2008

A Temperature-Aware Placement and Routing Algorithm Targeting 3D FPGAs.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

Fast Instruction Memory Hierarchy Power Exploration for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility.

[BibT_eX]

[DOI]

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007

Automated framework for partitioning DSP applications in hybrid reconfigurable platforms.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2007

Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement.

[BibT_eX]

[DOI]

J. Syst. Archit., 2007

Preface.

[BibT_eX]

[DOI]

Laurence Tianruo Yang

José G. Delgado-Frias

Integr., 2007

Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications.

[BibT_eX]

[DOI]

Integr., 2007

Systematic methodology for designing low power direct digital frequency synthesisers.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2007

Implementing cellular automata modeled applications on network-on-chip platforms.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2007, 2007

A software-supported methodology for designing high-performance 3D FPGA architectures.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2007, 2007

Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation.

[BibT_eX]

[DOI]

Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007

Systematic Data Structure Exploration of Multimedia and Network Applications realized Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

System-Level Application-Specific NoC Design for Network and Multimedia Applications.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Application - specific NoC platform design based on System Level Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

Component Based Library Implementation of Abstract Data Types for Resource Management Customization of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007

Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns.

[BibT_eX]

[DOI]

Stylianos Mamagkakis

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Designing Heterogeneous FPGAs with Multiple SBs.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2007

Data Structure Exploration of Dynamic Applications.

[BibT_eX]

[DOI]

Nikolaos S. Voros

Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006

Behavioral-Level Performance and Power Exploration of Data-Intensive Applications Mapped on Programmable Processors.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2006

A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Systematic dynamic memory management design methodology for reduced memory footprint.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers.

[BibT_eX]

[DOI]

Athanasios Kakarountas

J. Low Power Electron., 2006

Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems.

[BibT_eX]

[DOI]

Integr., 2006

Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance.

[BibT_eX]

[DOI]

Comput. Commun., 2006

Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Systematic design flow for dynamic data management in visual texture decoder of MPEG-4.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications.

[BibT_eX]

[DOI]

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A novel methodology for designing high-performance and low-energy FPGA routing architecture.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

An Estimation Methodology for Designing Instruction Cache Memory of Embedded Systems.

[BibT_eX]

[DOI]

Stylianos Mamagkakis

Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Energy-efficient dynamic memory allocators at the middleware level of embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006

Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Behavioral-level event-driven power management for DECT digital receivers.

[BibT_eX]

[DOI]

Microelectron. J., 2005

A complete platform and toolset for system implementation on fine-grain reconfigurable hardware.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2005

Memory power optimization of hardware implementations of multimedia applications onto FPGA platforms.

[BibT_eX]

[DOI]

Konstantinos Tatas

J. Embed. Comput., 2005

A Novel Division Algorithm and Architectures for Parallel and Sequential Processing.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2005

A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

A method for partitioning applications in hybrid reconfigurable architectures.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2005

Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications.

[BibT_eX]

[DOI]

Proceedings of the Wired/Wireless Internet Communications, Third International Conference, 2005

A Modified Spiral Search Algorithm and its Embedded Hardware Implementation.

[BibT_eX]

Proceedings of the International Enformatika Conference, 2005

Improving the Memory Bandwidth Utilization Using Loop Transformations.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2005

A modified spiral search motion estimation algorithm and its embedded system implementation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A methodology for partitioning DSP applications in hybrid reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow.

[BibT_eX]

[DOI]

Haroula Pournara

Ilias Pappas

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

The low power analogue and digital baseband processing parts of a novel multimode DECT/GSM/DCS1800 terminal.

[BibT_eX]

[DOI]

Microelectron. J., 2004

Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology.

[BibT_eX]

[DOI]

Proceedings of the Wired/Wireless Internet Communications, Second International Conference, 2004

A Novel Data-Path for Accelerating DSP Kernels.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications.

[BibT_eX]

[DOI]

Proceedings of the Computer Systems: Architectures, 2004

Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2004

A reusable IP FFT core for DSP applications.

[BibT_eX]

[DOI]

Spyros Blionas

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.

[BibT_eX]

[DOI]

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

A high performance data-path to accelerate DSP kernels.

[BibT_eX]

[DOI]

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

A novel coarse-grain reconfigurable data-path for accelerating DSP kernels.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Reducing memory accesses with a system-level design methodology in customized dynamic memory management.

[BibT_eX]

[DOI]

Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004

A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

2003

Data memory power optimization and performance exploration of embedded systems for implementing motion estimation algorithms.

[BibT_eX]

[DOI]

Real Time Imaging, 2003

Designing Low Power Direct Digital Frequency Synthesizers.

[BibT_eX]

Proceedings of the IFIP VLSI-SoC 2003, 2003

FPGA Architecture Design and Toolset for Logic Implementation.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design, 2003

Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms.

[BibT_eX]

[DOI]

Spyros Blionas

Proceedings of the Integrated Circuit and System Design, 2003

A methodology for implementing FIR filters and CAD tool development for designing RNS-based systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Alternative Direct Digital Frequency Synthesizer architectures with reduced memory size.

[BibT_eX]

[DOI]

Spyros Blionas

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

2002

A fast and accurate delay dependent method for switching estimation of large combinational circuits.

[BibT_eX]

[DOI]

J. Syst. Archit., 2002

Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Confronting violations of the TSCG(T) in low-power design.

[BibT_eX]

[DOI]

Athanasios Kakarountas

Kyriakos Papadomanolakis

Spiridon Nikolaidis

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A window-based color quantization technique and its embedded implementation.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Conference on Image Processing, 2002

A novel division algorithm for parallel and sequential processing.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A full adder based methodology for scaling operation in residue number system.

[BibT_eX]

[DOI]

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A window-based color quantization technique and its architecture implementation.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Digital Signal Processing, 2002

Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

A Code Transformation-Based Methodology for Improving I-Cache Performance of DSP Applications.

[BibT_eX]

[DOI]

Nikolaos D. Liveris

Proceedings of the 2002 Design, 2002

2001

A Fast and Accurate Method of Power Estimation for Logic Level Networks.

[BibT_eX]

[DOI]

VLSI Design, 2001

A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model.

[BibT_eX]

[DOI]

Spyros Theoharis

VLSI Design, 2001

Memory Hierarchy Optimization of Multimedia Applications on Programmable Embedded Cores 1.

[BibT_eX]

[DOI]

Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Performance comparison of DWT scheduling alternatives on programmable platforms.

[BibT_eX]

[DOI]

Giorgos P. Anagnostopoulos

I. Tagopoulos

Vassilis Spiliotopoulos

Spyridoula K. Vasilopoulou

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

The circuit design of multiple-valued logic voltage-mode adders.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A CAD tool for architecture level exploration and automatic generation of RNS converters.

[BibT_eX]

[DOI]

D. J. Soudris

Minas Dasygenis

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Power, performance and area exploration of block matching algorithms mapped on programmable processors.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Conference on Image Processing, 2001

Designing low-power energy recovery adders based on pass transistor logic.

[BibT_eX]

[DOI]

Vasilis F. Pavlidis

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

The low power baseband processing parts of a novel dual mode DECT/GSM terminal.

[BibT_eX]

[DOI]

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Data and instruction memory exploration of embedded systems for multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2001

2000

Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers.

[BibT_eX]

[DOI]

Athanasios Kakarountas

Proceedings of the Integrated Circuit Design, 2000

Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit Design, 2000

A methodology for the behavioral-level event-driven power management of digital receivers.

[BibT_eX]

[DOI]

Spyros Theoharis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Low power design of a multi-mode transceiver.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Designing RNS and QRNS full adder based converters.

[BibT_eX]

[DOI]

D. J. Soudris

Minas Dasygenis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A New Method for Low Power Design of Two-Level Logic Circuits.

[BibT_eX]

[DOI]

Spyros Theoharis

VLSI Design, 1999

An efficient probabilistic method for logic circuits using real delay gate model.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

The VLSI implementation of a baseband receiver for DECT-based portable applications.

[BibT_eX]

[DOI]

Efstathios D. Kyriakis-Bitzaros

Thanos Stouraitis

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

The design of low power multiple-valued logic encoder and decoder circuits.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

A new adiabatic technique for designing low power array architectures.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Estimation of power dissipation in glitching using complex-time cellular automata.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1998

Multiple-Valued Logic Voltage-Mode Storage Circuits Based On True-Single-Phase Clocked Logic.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1996

Transformation of Nested Loops into Uniform Recurrences and their Mapping to Regular Processor Arrays.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1996

A novel approach for reducing the switching activity in two-level logic circuits.

[BibT_eX]

[DOI]

Odysseas G. Koufopavlou

Costas E. Goutis

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

Low-power design of array architectures.

[BibT_eX]

[DOI]

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1993

A Systematic Methodology for Designing Multilevel Systolic Architectures.

[BibT_eX]

P. D. Georgakopoulos

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Methodology for the Design of Signed-digit DSP Processors.

[BibT_eX]

Vassilis Paliouras

Thanos Stouraitis

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Systematic design of full adder-based architectures for convolution.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 1993

1992

Systematic development of architectures for multidimensional DSP using the residue number system.

[BibT_eX]

[DOI]

Vassilis Paliouras

Thanos Stouraitis

Proceedings of the 1992 IEEE International Conference on Acoustics, 1992

1991

Mapping iterative algorithims on regular processor arrays without using uniform recurrent equations.

[BibT_eX]

[DOI]

Dimitrios J. Soudris

Michael K. Birbas

Costas E. Goutis

Microprocessing and Microprogramming, 1991

Direct mapping of nested loops on piecewise regular processor arrays.

[BibT_eX]

Michael K. Birbas