Dimitrios Karayiannis

According to our database, Dimitrios Karayiannis authored at least 9 papers between 1995 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

A fast nonenumerative automatic test pattern generator for pathdelay faults.

Spyros Tragoudas, Dimitrios Karayiannis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

1998

Timing-Driven Circuit Implementation.

Dimitrios Karayiannis, Spyros Tragoudas

VLSI Design, 1998

Clustering Network Modules with Different Implementations for Delay Minimization.

Dimitrios Karayiannis, Spyros Tragoudas

VLSI Design, 1998

A Nonenumerative ATPG for Functionally Sensitizable Path Delay Faults.

Dimitrios Karayiannis, Spyros Tragoudas

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms.

Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Implementing and clustering modules with complex delays.

Spyros Tragoudas, Dimitrios Karayiannis

Integr., 1997

Nonenumerative Path Delay Fault Coverage Estimation with Optimal Algorithms.

Dimitrios Kagaris, Spyros Tragoudas, Dimitrios Karayiannis

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

ATPD: An Automatic Test Pattern Generator for Path Delay Faults.

Dimitrios Karayiannis, Spyros Tragoudas

Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995

Uniform area timing-driven circuit implementation.

Dimitrios Karayiannis, Spyros Tragoudas

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995