Dimitrios Garyfallou

According to our database, Dimitrios Garyfallou authored at least 19 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A low-rank balanced truncation approach for large-scale RLCk model order reduction based on extended Krylov subspace and a frequency-aware convergence criterion.

Christos Giamouzis, Dimitrios Garyfallou, Nestoras E. Evmorfopoulos, George I. Stamoulis

CoRR, 2024

MORCIC: Model Order Reduction Techniques for Electromagnetic Models of Integrated Circuits.

Dimitrios Garyfallou, Athanasios Stefanou, Christos Giamouzis, Moschos Antoniadis, Georgios Chararas, Konstantinos Chatzis, Dimitris Samaras, Rafaela Themeli, Anastasios Michailidis, Vasiliki Gogolou, Nikos Zachos, Nestor E. Evmorfopoulos, Thomas Noulis, Vasilis F. Pavlidis, Alkiviadis Hatzopoulos, Elpida Chatzineofytou, Yiannis Moisiadis

CoRR, 2024

A learning-based method for performance optimization of timing analysis.

Anastasis Vagenas, Dimitrios Garyfallou, Nestoras E. Evmorfopoulos, George I. Stamoulis

Proceedings of the 20th International Conference on Synthesis, 2024

Low-rank balanced truncation of RLCk models via frequency-aware rational Krylov-based projection.

Christos Giamouzis, Dimitrios Garyfallou, Georgios I. Stamoulis, Nestoras E. Evmorfopoulos

Proceedings of the 20th International Conference on Synthesis, 2024

Advanced gate-level glitch modeling using ANNs.

Anastasis Vagenas, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, George I. Stamoulis

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023

Reduction of large-scale RLCk models via low-rank balanced truncation.

Christos Giamouzis, Dimitrios Garyfallou, Anastasis Vagenas, Nestor E. Evmorfopoulos

CoRR, 2023

Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential.

Pavlos Stoikos, George Floros, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis

Proceedings of the 19th International Conference on Synthesis, 2023

Accurate Soft Error Rate Evaluation Using Event-Driven Dynamic Timing Analysis.

Georgios Ioannis Paliaroutis, Pelopidas Tsoumanis, Dimitrios Garyfallou, Anastasis Vagenas, Nestoras E. Evmorfopoulos, Georgios I. Stamoulis

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

A Fast Semi-Analytical Approach for Transient Electromigration Analysis of Interconnect Trees Using Matrix Exponential.

Pavlos Stoikos, George Floros, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, George I. Stamoulis

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

The Extended and Asymmetric Extended Krylov Subspace in Moment-Matching-Based Order Reduction of Large Circuit Models.

Pavlos Stoikos, Dimitrios Garyfallou, George Floros, Nestor E. Evmorfopoulos, George I. Stamoulis

CoRR, 2022

Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance.

Dimitrios Garyfallou, Anastasis Vagenas, Charalampos Antoniadis, Yehia Massoud, George I. Stamoulis

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021

Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance.

Dimitrios Garyfallou, Stavros Simoglou, Nikolaos Sketopoulos, Charalampos Antoniadis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, George I. Stamoulis

IEEE Trans. Very Large Scale Integr. Syst., 2021

Exploiting Extended Krylov Subspace for the Reduction of Regular and Singular Circuit Models.

Chrysostomos Chatzigeorgiou, Dimitrios Garyfallou, George Floros, Nestor E. Evmorfopoulos, George I. Stamoulis

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation.

Dimitrios Garyfallou, Ioannis Tsiokanos, Nestor E. Evmorfopoulos, Georgios I. Stamoulis, Georgios Karakonstantis

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

2019

A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects.

Dimitrios Garyfallou, Charalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis

Proceedings of the 16th International Conference on Synthesis, 2019

2018

A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPU s.

Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis

Proceedings of the 15th International Conference on Synthesis, 2018

Large scale circuit simulation exploiting combinatorial multigrid on massively parallel architectures.

Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis

Proceedings of the 7th International Conference on Modern Circuits and Systems Technologies, 2018

EVT-based worst case delay estimation under process variation.

Charalampos Antoniadis, Dimitrios Garyfallou, Nestor E. Evmorfopoulos, Georgios I. Stamoulis

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Heuristics to Augment the Performance of Tetris Legalization: Making a Fast but Inferior Method Competitive.

Antonios N. Dadaliaris, Panagiotis Oikonomou, Maria G. Koziri, Evangelia Nerantzaki, Yannis Hatzaras, Dimitrios Garyfallou, Thanasis Loukopoulos, Georgios I. Stamoulis

J. Low Power Electron., 2017