Dimitra Papagiannopoulou

According to our database, Dimitra Papagiannopoulou authored at least 12 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2019

IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM.

Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures.

Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar

Int. J. Parallel Program., 2018

2017

Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency.

Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar

ACM Trans. Embed. Comput. Syst., 2017

Evaluating critical bits in arithmetic operations due to timing violations.

Sungseob Whang, Tymani Rachford, Dimitra Papagiannopoulou, Tali Moreshet, R. Iris Bahar

Proceedings of the 2017 IEEE High Performance Extreme Computing Conference, 2017

2016

Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.

Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar

Proceedings of the 2016 International Conference on Compilers, 2016

2015

Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems.

Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar

ACM Trans. Embed. Comput. Syst., 2015

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution.

Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Speculative synchronization for coherence-free embedded NUMA architectures.

Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

2013

Flexible data allocation for scratch-pad memories to reduce NBTI effects.

Dimitra Papagiannopoulou, Patipan Prasertsom, R. Iris Bahar

Proceedings of the International Symposium on Quality Electronic Design, 2013

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs.

Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini

Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013

2012

NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems.

Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera

J. Electron. Test., 2012

2011

NBTI-aware data allocation strategies for scratchpad memory based embedded systems.

Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera

Proceedings of the 12th Latin American Test Workshop, 2011