Dilip Kumar Maity

According to our database, Dilip Kumar Maity authored at least 7 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Built-in Self-prevention (BISP) for runtime ageing effects of TSVs in 3D ICs.

Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri

Integr., January, 2024

2022

A Cost-Effective Built-In Self-Test Mechanism for Post-Manufacturing TSV Defects in 3D ICs.

Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri

ACM J. Emerg. Technol. Comput. Syst., 2022

2021

TSV-Cluster Defect Tolerance Using Tree-Based Redundancy for Yield Improvement of 3-D ICs.

Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2019

Identification of Random/Clustered TSV Defects in 3D IC During Pre-Bond Testing.

Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri

J. Electron. Test., 2019

2018

Identification of Faulty TSVs in 3D IC During Pre-Bond Testing.

Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri

Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Identification of Faulty TSV with a Built-In Self-Test Mechanism.

Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri, Hafizur Rahaman

Proceedings of the 27th IEEE Asian Test Symposium, 2018

2017

Faulty TSVs Identification in 3D IC Using Pre-bond Testing.

Dilip Kumar Maity, Surajit Kumar Roy, Chandan Giri

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017