Dilip K. Bhavsar

According to our database1, Dilip K. Bhavsar authored at least 23 papers between 1981 and 2011.

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Bibliography

2011
Harmony Widget for X-free scan testing.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

Test access and the testability features of the Poulson multi-core Intel Itanium® processor.
Proceedings of the 2011 IEEE International Test Conference, 2011

2005
A Built-in Self-Test Method for Write-only Content Addressable Memories.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2003
Testability Features of the Alpha 21364 Microprocessor.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

2002
Scan Islands - A Scan Partitioning Architecture and its Implementation on the Alpha 21364 Processor.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001
Scan Wheel - A Technique for Interfacing a High Speed Scan-Path with a Slow Speed Tester.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000
Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability.
IEEE Des. Test Comput., 2000

1999
ITC 99 Panels.
IEEE Des. Test Comput., 1999

An algorithm for row-column self-repair of RAMs and its implementation in the Alpha 21264.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
ITC 97 Panel Sessions.
IEEE Des. Test Comput., 1998

A highly testable and diagnosable fabrication process test chip.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Testability access of the high speed test features in the Alpha 21264 microprocessor.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Alpha 21164 Testability Strategy.
IEEE Des. Test Comput., 1997

1994
Testability Strategy of the ALPHA AXP 21164 Microprocessor.
Proceedings of the Proceedings IEEE International Test Conference 1994, 1994

1991
Testing Interconnections to Static RAMs.
IEEE Des. Test Comput., 1991

An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1986
A New Economical Implementation for Scannable Flip-Flops in MOS.
IEEE Des. Test, 1986

1985
"Concatenable Polydividers": Bit-Sliced LFSR Chips for Board Self-Test.
Proceedings of the Proceedings International Test Conference 1985, 1985

1984
Can We Eliminate Fault Escape in Self-Testing by Polynomial Division (Signature Analysis) ?
Proceedings of the Proceedings International Test Conference 1984, 1984

1983
Design For Test Calculus: An algorithm for DFT rules checking.
Proceedings of the 20th Design Automation Conference, 1983

1981
Self-Testing by Polynomial Division.
Proceedings of the Proceedings International Test Conference 1981, 1981


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