Dihang Yang

According to our database, Dihang Yang authored at least 4 papers between 2019 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise.

David Murphy, Dihang Yang, Hooman Darabi, Arya Behzad

IEEE J. Solid State Circuits, September, 2023

2022

A Harmonic-Mixing PLL Architecture for Millimeter-Wave Application.

Dihang Yang, David Murphy, Hooman Darabi, Arya Behzad, Asad A. Abidi, Stephen Au, Sraavan R. Mundlapudi, Kejian Shi, Weiyu Leng

IEEE J. Solid State Circuits, 2022

A Sub-100MHz Reference-Driven 25-to-28GHz Fractional-N PLL with -250dB FoM.

Dihang Yang, David Murphy, Hooman Darabi, Arya Behzad, Asad A. Abidi, Stephen Au, Sraavan R. Mundlapudi, Kejian Shi, Weiyu Leng

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2019

A Calibration-Free Triple-Loop Bang-Bang PLL Achieving 131fsrms Jitter and-70dBc Fractional Spurs.

Dihang Yang, Asad A. Abidi, Hooman Darabi, Hao Xu, David Murphy, Hao Wu, Zhaowen Wang

Proceedings of the IEEE International Solid- State Circuits Conference, 2019