Dieter F. Wendel
According to our database1,
Dieter F. Wendel
authored at least 24 papers
between 2000 and 2017.
Collaborative distances:
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Bibliography
2017
A system of array families and synthesized soft arrays for the POWER9™ processor in 14nm SOI FinFET technology.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A 4GHz, low latency TCAM in 14nm SOI FinFET technology using a high performance current sense amplifier for AC current surge reduction.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
5.1 POWER8<sup>TM</sup>: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
The POWER8<sup>TM</sup> processor: Designed for big data, analytics, and cloud environments.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE J. Solid State Circuits, 2011
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
The implementation of POWER7<sup>TM</sup>: A highly parallel and scalable multi-core high-end server processor.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2008
Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V.
IEEE J. Solid State Circuits, 2008
2007
Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
IEEE J. Solid State Circuits, 2006
Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor.
IEEE J. Solid State Circuits, 2006
Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2001
IEEE J. Solid State Circuits, 2001
2000
IBM J. Res. Dev., 2000