Diego Puschini

Orcid: 0000-0001-9614-9122

According to our database1, Diego Puschini authored at least 36 papers between 2005 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2017
AES Datapath Optimization Strategies for Low-Power Low-Energy Multisecurity-Level Internet-of-Things Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Adaptive Architectures, Circuits and Technology Solutions for Future IoT Systems.
J. Low Power Electron., 2017

2016
Tracking BTI and HCI effects at circuit-level in adaptive systems.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Multi-sensor fusion of occupancy grids based on integer arithmetic.
Proceedings of the 2016 IEEE International Conference on Robotics and Automation, 2016

Ultra low-power and low-energy 32-bit datapath AES architecture for IoT applications.
Proceedings of the International Conference on IC Design and Technology, 2016

Integration of multi-sensor occupancy grids into automotive ECUs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Energy management via PI control for data parallel applications with throughput constraints.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Evaluation and mitigation of aging effects on a digital on-chip voltage and temperature sensor.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Energy-efficient control through power mode placement with discrete DVFS and Body Bias.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Intelligent Vehicle Perception: Toward the Integration on Embedded Many-core.
Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2015

Design and implementation of a Predictive Control strategy for power management of a wireless sensor network.
Proceedings of the 14th European Control Conference, 2015

Real-time power-efficient integration of multi-sensor occupancy grid on many-core.
Proceedings of the 2015 IEEE International Workshop on Advanced Robotics and its Social Impacts, 2015

2014
A Fine-Grain Variation-Aware Dynamic Vdd-Hopping AVFS Architecture on a 32 nm GALS MPSoC.
IEEE J. Solid State Circuits, 2014

Dynamic power management in a wireless sensor network using predictive control.
Proceedings of the IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, Dallas, TX, USA, October 29, 2014

Power management through DVFS and dynamic body biasing in FD-SOI circuits.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Multivariable voltage and frequency control for DVFS management.
Proceedings of the 2014 IEEE Conference on Control Applications, 2014

2013
Coupled voltage and frequency control for DVFS management.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A fine grain variation-aware dynamic Vdd-hopping AVFS architecture on a 32nm GALS MPSoC.
Proceedings of the ESSCIRC 2013, 2013

Event-based DVFS control in GALS-ANoC MPSoCs.
Proceedings of the American Control Conference, 2013

2012
Integrated architecture exploration workflow: A NoC-based case study.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Advanced coupled voltage-frequency control for power efficient DVFS management.
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012

2011
Architecture and Robust Control of a Digital Frequency-Locked Loop for Fine-Grain Dynamic Voltage and Frequency Scaling in Globally Asynchronous Locally Synchronous Structures.
J. Low Power Electron., 2011

Low-Cost Dynamic Voltage and Frequency Management Based upon Robust Control Techniques under Thermal Constraints.
Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011

Sustainability through massively integrated computing: Are we ready to break the energy efficiency wall for single-chip platforms?
Proceedings of the Design, Automation and Test in Europe, 2011

Optimal and robust saturated control for a Clock Generator.
Proceedings of the 50th IEEE Conference on Decision and Control and European Control Conference, 2011

An Introduction to Multi-Core System on Chip - Trends and Challenges.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Dynamic Energy Optimization in Network-on-Chip-Based System-on-Chips.
J. Low Power Electron., 2010

2009
Adaptive energy-aware latency-constrained DVFS policy for MPSoC.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
A Game-Theoretic Approach for Run-Time Distributed Optimization on MP-SoC.
Int. J. Reconfigurable Comput., 2008

Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Temperature-Aware Distributed Run-Time Optimization on MP-SoC Using Game Theory.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Convergence analysis of run-time distributed optimization on adaptive systems using game theory.
Proceedings of the FPL 2008, 2008

2006
A Comparison between NoC and Bus Architectures Based on a Real-Application.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

2005
Hybrid sensor network and fusion algorithm for sound source localization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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