Didier Lattard
According to our database1,
Didier Lattard
authored at least 47 papers
between 1988 and 2024.
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Bibliography
2024
First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2021
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021
2020
Ultra-High-density 3D vertical RRAM with stacked JunctionLess nanowires for In-Memory-Computing applications.
CoRR, 2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D IC.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Test Solutions for High Density 3D-IC Interconnects - Focus on SRAM-on-Logic Partitioning.
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Misalignment Analysis and Electrical Performance of High Density 3D-IC interconnects.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
Merging PDKs to Build a Design Environment for 3D Circuits: Methodology, Challenges and Limitations.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
Fine pitch 3D interconnections with hybrid bonding technology: From process robustness to reliability.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
A review on opportunities brought by 3D-monolithic integration for CMOS device and digital circuit.
Proceedings of the 2018 International Conference on IC Design & Technology, 2018
Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
BISTs for post-bond test and electrical analysis of high density 3D interconnect defects.
Proceedings of the 23rd IEEE European Test Symposium, 2018
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links.
IEEE J. Solid State Circuits, 2017
Innovative structures to test bonding alignment and characterize high density interconnects in 3D-IC.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
2016
IEEE Des. Test, 2016
8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016
2015
Design and implementation of a closed-loop controller for a self-adaptive IEEE 802.15.4 DBB.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
An energy-efficient IEEE 802.15.4 tunable digital baseband targeting self-adaptive WPANs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Fine-grain DVFS and AVFS techniques for complex SoC design: An overview of architectural solutions through technology nodes.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014
Proceedings of the 9th International Symposium on Communication Systems, 2014
2012
An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip.
Softw. Pract. Exp., 2012
IPSJ Trans. Syst. LSI Des. Methodol., 2012
Proceedings of the Sensors, 2012
2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
High level modelling and performance evaluation of address mapping in NAND flash memory.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Proceedings of the ESSCIRC 2008, 2008
2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Trends in complex SoC Design: From technology variability to multiprocessor architectures.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2005
Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2.
Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005
Proposition of a benchmark for evaluation of cores mapping onto NoC architectures.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005
1996
A Data Dependent Architecture Based on Seeded Region Growing Strategy for Advanced Morphological Operators.
Proceedings of the 3th International Symposium on Mathematical Morphology and its Applications to Image and Signal Processing, 1996
1991
CVGIP Graph. Model. Image Process., 1991
1990
Massively parallel architecture: application to neural net emulation and image reconstruction.
Proceedings of the Application Specific Array Processors, 1990
1989
Architecture massivement parallèle : un réseau de cellules intégré pour la reconstruction d'images. (Massively parallel architecture : and integrated cellular network for image reconstruction).
PhD thesis, 1989
1988
Proceedings of IAPR Workshop on Computer Vision, 1988
Proceedings of the Advances in Computer Graphics Hardware III (Eurographics'88 Workshop), 1988