Didier Demigny
According to our database1,
Didier Demigny
authored at least 26 papers
between 1995 and 2010.
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Bibliography
2010
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures.
Int. J. Reconfigurable Comput., 2010
Mesh and Fat-Tree comparison for dynamically reconfigurable applications.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010
2009
A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
2008
Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing.
J. Real Time Image Process., 2008
2006
Clear Stream towards Dynamically Reconfigurable Systems on Chip.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006
2005
Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce.
Tech. Sci. Informatiques, 2005
2004
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.
Proceedings of the Computer Systems: Architectures, 2004
Design flexibility using fpga dynamical reconfiguration.
Proceedings of the 2004 International Conference on Image Processing, 2004
2003
Real Time Imaging, 2003
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003
A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
2002
2001
Two ASIC for Low and Middle Levels of Real Time Image Processing.
Proceedings of the SOC Design Methodologies, 2001
Reconfigurable Architecture Using High Speed FPGA.
Proceedings of the SOC Design Methodologies, 2001
Fast Recursive Implementation of the Gaussian Filter.
Proceedings of the SOC Design Methodologies, 2001
2000
Proceedings of the 2000 International Conference on Image Processing, 2000
Proceedings of the Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), 2000
1998
Extension of Canny's Discrete Criteria to Second Derivative Filters Towards a Unified Approach.
Proceedings of the 1998 IEEE International Conference on Image Processing, 1998
1997
A Discrete Expression of Canny's Criteria for Step Edge Detector Performances Evaluation.
IEEE Trans. Pattern Anal. Mach. Intell., 1997
Proceedings of the Proceedings 1997 International Conference on Image Processing, 1997
1996
An effective resolution definition or how to choose an edge detector, its scale parameter and the threshold?
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996
1995
Evaluation of edge detectors performances with a discrete expression of Canny's criteria.
Proceedings of the Proceedings 1995 International Conference on Image Processing, 1995