Dian Zhou
Orcid: 0000-0002-2648-5232
According to our database1,
Dian Zhou
authored at least 203 papers
between 1989 and 2024.
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Bibliography
2024
ROI-HIT: Region of Interest-Driven High-Dimensional Microarchitecture Design Space Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024
D<sup>3</sup>PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing.
ACM Trans. Design Autom. Electr. Syst., May, 2024
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2024
Comput. Animat. Virtual Worlds, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
EVDMARL: Efficient Value Decomposition-based Multi-Agent Reinforcement Learning with Domain-Randomization for Complex Analog Circuit Design Migration.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
HiMOSS: A Novel High-dimensional Multi-objective Optimization Method via Adaptive Gradient-Based Subspace Sampling for Analog Circuit Sizing.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Artisan: Automated Operational Amplifier Design via Domain-specific Large Language Model.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper).
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Quantitative Analysis of Tidal Creek Evolution and Vegetation Variation in Silting Muddy Flats on the Yellow Sea.
Remote. Sens., November, 2023
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., February, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
Identification and Evolution of Soil Organic Carbon Density Caused by Coastal Rapid Siltation Based on Imaging Spectroscopy.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2023
Sensors, 2023
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
ACM Trans. Design Autom. Electr. Syst., 2022
Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative.
IEEE J. Biomed. Health Informatics, 2022
An Efficient Batch-Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multiobjective Acquisition Ensemble.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Fast Statistical Analysis of Rare Failure Events With Truncated Normal Distribution in High-Dimensional Variation Space.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Predicting the quality of answers with less bias in online health question answering communities.
Inf. Process. Manag., 2022
LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces.
Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A High-Precision Stochastic Solver for Steady-State Thermal Analysis with Fourier Heat Transfer Robin Boundary Conditions.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma sampling.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble.
CoRR, 2021
IEEE Access Special Section Editorial: Smart Health Sensing and Computational Intelligence: From Big Data to Big Impacts.
IEEE Access, 2021
IEEE Access Special Section Editorial: Advanced Information Sensing and Learning Technologies for Data-Centric Smart Health Applications.
IEEE Access, 2021
Bayesian Optimization Approach for Analog Circuit Design Using Multi-Task Gaussian Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
NeurFill: Migrating Full-Chip CMP Simulators to Neural Networks for Model-Based Dummy Filling Synthesis.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
A Robust Batch Bayesian Optimization for Analog Circuit Synthesis via Local Penalization.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
High-Dimensional Bayesian Optimization for Automated Analog Circuit Design via Add-Graph Structure.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
A Fast Aging-aware Static Timing Analysis Prediction Frame of Digital Integrated Circuits.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
ACM Trans. Design Autom. Electr. Syst., 2020
Efficient Statistical Analysis for Correlated Rare Failure Events via Asymptotic Probability Approximation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Efficient Parametric Yield Estimation Over Multiple Process Corners via Bayesian Inference Based on Bernoulli Distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Efficient Rare Failure Analysis Over Multiple Corners via Correlated Bayesian Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Neural Comput. Appl., 2020
CoRR, 2020
Application of Deep Learning Algorithm in Feature Mining and Rapid Identification of Colorectal Image.
IEEE Access, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Multi-Corner Parametric Yield Estimation via Bayesian Inference on Bernoulli Distribution with Conjugate Prior.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 7th International Conference on Dependable Systems and Their Applications, 2020
An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process Modeling.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
An Efficient Asynchronous Batch Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
An Efficient and Robust Yield Optimization Method for High-dimensional SRAM Circuits.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
An Efficient FPGA Implementation of Orthogonal Matching Pursuit With Square-Root-Free QR Decomposition.
IEEE Trans. Very Large Scale Integr. Syst., 2019
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access via Data Reuse.
ACM Trans. Reconfigurable Technol. Syst., 2019
Graph-Constrained Sparse Performance Modeling for Analog Circuit Optimization via SDP Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
Proceedings of the IEEE Symposium Series on Computational Intelligence, 2019
Efficient Performance Trade-off Modeling for Analog Circuit based on Bayesian Neural Network.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the 6th International Conference on Dependable Systems and Their Applications, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
An Efficient FPGA-based Floating Random Walk Solver for Capacitance Extraction using SDAccel.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit Synthesis.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2018
Thermal Stress and Reliability Analysis of TSV-Based 3-D ICs With a Novel Adaptive Strategy Finite Element Method.
IEEE Trans. Very Large Scale Integr. Syst., 2018
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2018
ACM Trans. Design Autom. Electr. Syst., 2018
An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Interlayer Cooling Network Design for High-Performance 3D ICs Using Channel Patterning and Pruning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Efficient Yield Optimization for Analog and SRAM Circuits via Gaussian Process Regression and Adaptive Yield Estimation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
A novel single-arm-worn 24 h heart disease monitor empowered by machine intelligence.
Biomed. Signal Process. Control., 2018
Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design.
Proceedings of the 35th International Conference on Machine Learning, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuits.
Proceedings of the 55th Annual Design Automation Conference, 2018
A general graph based pessimism reduction framework for design optimization of timing closure.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
High-Dimensional and Multiple-Failure-Region Importance Sampling for SRAM Yield Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2017
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst., 2017
Optimization and Quality Estimation of Circuit Design via Random Region Covering Method.
ACM Trans. Design Autom. Electr. Syst., 2017
C-YES: An Efficient Parametric Yield Estimation Approach for Analog and Mixed-Signal Circuits Based on Multicorner-Multiperformance Correlations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Improved Tangent Space-Based Distance Metric for Lithographic Hotspot Classification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
A Novel Framework for Motion-Tolerant Instantaneous Heart Rate Estimation by Phase-Domain Multiview Dynamic Time Warping.
IEEE Trans. Biomed. Eng., 2017
An efficient and robust method to determine the optimal tap coefficients of high speed FIR equalizer.
Sci. China Inf. Sci., 2017
HeartID: A Multiresolution Convolutional Neural Network for ECG-Based Biometric Human Identification in Smart Health Applications.
IEEE Access, 2017
A Machine Learning-Empowered System for Long-Term Motion-Tolerant Wearable Monitoring of Blood Pressure and Heart Rate With Ear-ECG/PPG.
IEEE Access, 2017
Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017
Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017
Proceedings of the 2017 IEEE International Conference on Cybernetics and Intelligent Systems (CIS) and IEEE Conference on Robotics, 2017
Proceedings of the 2017 IEEE International Symposium on Parallel and Distributed Processing with Applications and 2017 IEEE International Conference on Ubiquitous Computing and Communications (ISPA/IUCC), 2017
Efficient spectral graph sparsification via Krylov-subspace based spectral perturbation analysis.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An efficient leakage-aware thermal simulation approach for 3D-ICs using corrected linearized model and algebraic multigrid.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
A yield-enhanced global optimization methodology for analog circuit based on extreme value theory.
Sci. China Inf. Sci., 2016
IEEE Comput. Archit. Lett., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Fast compressive sensing reconstruction algorithm on FPGA using Orthogonal Matching Pursuit.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Efficient statistical analysis for correlated rare failure events via asymptotic probability approximation.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Efficient multiple starting point optimization for automated analog circuit optimization via recycling simulation data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Efficient performance modeling via Dual-Prior Bayesian Model Fusion for analog and mixed-signal circuits.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Efficient performance modeling of analog integrated circuits via kernel density based sparse regression.
Proceedings of the 53rd Annual Design Automation Conference, 2016
An efficient trajectory-based algorithm for model order reduction of nonlinear systems via localized projection and global interpolation.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework.
IEEE Trans. Very Large Scale Integr. Syst., 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2013
Near-Field Communication Transceiver System Modeling and Analysis Using SystemC/SystemC-AMS With the Consideration of Noise Issues.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
Cumulative Probability Distribution Model for Evaluating User Behavior Prediction Algorithms.
Proceedings of the International Conference on Social Computing, SocialCom 2013, 2013
Proceedings of the E-Commerce and Web Technologies - 14th International Conference, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design.
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
An Efficient Method for Evaluating Analog Circuit Performance Bounds Under Process Variations.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Performance Analysis of Flow-Based Traffic Splitting Strategy on Cluster-Mesh Sensor Networks.
Int. J. Distributed Sens. Networks, 2012
A context-aware computing mediated dynamic service composition and reconfiguration for ubiquitous environment.
Proceedings of the 3rd IEEE International Conference on the Internet of Things, 2012
2011
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 2011 IEEE Wireless Communications and Networking Conference, 2011
Worst case analysis for evaluating VLSI circuit performance bounds using an optimization method.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
A novel approach to estimate the impact of analog circuit performance based on the small signal model under process variations.
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
Proceedings of the IEEE 22nd International Symposium on Personal, 2011
An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
IEICE Trans. Inf. Syst., 2010
Stochastic Sparse-Grid Collocation Algorithm for Steady-State Analysis of Nonlinear System with Process Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
2009
Proceedings of the 69th IEEE Vehicular Technology Conference, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
PER performance enhancement through antenna and transceiver co-design for multi-band OFDM UWB communication.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
An Efficient Multi-protocol RFID Interrogator Baseband Processor based on a Reconfigurable Architecture.
Proceedings of the International Conference on Embedded Software and Systems, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Sci. China Ser. F Inf. Sci., 2007
RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the Future Generation Communication and Networking, 2007
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process Variations.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
ACM Trans. Design Autom. Electr. Syst., 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A Spectral Stochastic Collocation Method for Capacitance Extraction of Interconnects with Process Variations.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
J. Comput. Sci. Technol., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
A closed-form phase noise solution for an ideal LC oscillator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Two-sided projection method in variational equation model order reduction of nonlinear circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Frequency driven repeater insertion for deep submicron.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Steady-State Analysis of Nonlinear Circuits Using Discrete Singular Convolution Method.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Analog circuit behavioral modeling via wavelet collocation method with auto-companding.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Behavioral modeling for analog system-level simulation by wavelet collocation method.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
An error distribution based nonlinear companding method for analog behavioral modeling via wavelet approximation.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
An efficient Sylvester equation solver for time domain circuit simulation by wavelet collocation method.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003
2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the IEEE International Conference on Acoustics, 2002
2001
An efficient balanced truncation realization algorithm for interconnect model order reduction.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 1999 International Symposium on Physical Design, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1997
Proceedings of the 1997 International Symposium on Physical Design, 1997
1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
1993
A Two-pole Circuit Model for VLSI High-speed Interconnection.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Propagation Delay in RLC Interconnection Networks.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
1990
Integr., 1990
1989
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989