Di Liu

Orcid: 0000-0002-4365-2768

Affiliations:
  • Nanyang Technological University, HP-NTU Manufacturing Lab, Singapore
  • Yunnan University, National Pilot School of Software, Kunming, China (2017 - 2020)
  • Leiden University, The Netherlands (PhD 2017)


According to our database1, Di Liu authored at least 64 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
FedTR: Federated Learning Framework with Transfer Learning for Industrial Visual Inspection.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Double-Win NAS: Towards Deep-to-Shallow Transformable Neural Architecture Search for Intelligent Embedded Systems.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Pearls Hide Behind Linearity: Simplifying Deep Convolutional Networks for Embedded Hardware Systems via Linearity Grafting.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
Efficient FPGA-Based Sparse Matrix-Vector Multiplication With Data Reuse-Aware Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

EdgeCompress: Coupling Multidimensional Model Compression and Dynamic Inference for EdgeAI.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

Improving robustness of convolutional neural networks using element-wise activation scaling.
Future Gener. Comput. Syst., December, 2023

On Hardware-Aware Design and Optimization of Edge Intelligence.
IEEE Des. Test, December, 2023

Energy-efficient computation offloading strategy with task priority in cloud assisted multi-access edge computing.
Future Gener. Comput. Syst., November, 2023

OCAP: On-device Class-Aware Pruning for personalized edge DNN models.
J. Syst. Archit., September, 2023

LightNAS: On Lightweight and Scalable Neural Architecture Search for Embedded Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Latency-constrained DNN architecture learning for edge systems using zerorized batch normalization.
Future Gener. Comput. Syst., May, 2023

SurgeNAS: A Comprehensive Surgery on Hardware-Aware Differentiable Neural Architecture Search.
IEEE Trans. Computers, April, 2023

FAT: An In-Memory Accelerator With Fast Addition for Ternary Weight Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

EMNAPE: Efficient Multi-Dimensional Neural Architecture Pruning for EdgeAI.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Towards Efficient Convolutional Neural Network for Embedded Hardware via Multi-Dimensional Pruning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Crossbar-Aligned & Integer-Only Neural Network Compression for Efficient in-Memory Acceleration.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

MUGNoC: A Software-Configured Multicast-Unicast-Gather NoC for Accelerating CNN Dataflows.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Layerwise Security Protection for Deep Neural Networks in Industrial Cyber Physical Systems.
IEEE Trans. Ind. Informatics, 2022

Toward the Predictability of Dynamic Real-Time DNN Inference.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Designing Efficient DNNs via Hardware-Aware Neural Architecture Search and Beyond.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

CARTAD: Compiler-Assisted Reinforcement Learning for Thermal-Aware Task Scheduling and DVFS on Multicores.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Bringing AI to edge: From deep learning's perspective.
Neurocomputing, 2022

EDLAB: A Benchmark for Edge Deep Learning Accelerators.
IEEE Des. Test, 2022

Improving Robustness of Convolutional Neural Networks Using Element-Wise Activation Scaling.
CoRR, 2022

Collate: Collaborative Neural Network Learning for Latency-Critical Edge Systems.
Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Smart Scissor: Coupling Spatial Redundancy Reduction and CNN Compression for Embedded Hardware.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Once For All Skip: Efficient Adaptive Deep Neural Networks.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

You only search once: on lightweight differentiable architecture search for resource-constrained embedded platforms.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Work-in-Progress: What to Expect of Early Training Statistics? An Investigation on Hardware-Aware Neural Architecture Search.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022

Efficient On-Device Incremental Learning by Weight Freezing.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

HACScale: Hardware-Aware Compound Scaling for Resource-Efficient DNNs.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021
Energy-Aware Task Offloading and Resource Allocation for Time-Sensitive Services in Mobile Edge Computing Systems.
IEEE Trans. Veh. Technol., 2021

Fairness-Aware Task Scheduling and Resource Allocation in UAV-Enabled Mobile Edge Computing Networks.
IEEE Trans. Green Commun. Netw., 2021

Reaching consensus in decentralized coordination of distributed microservices.
Comput. Networks, 2021

Partial order based non-preemptive communication scheduling towards real-time networks-on-chip.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

Optimized Data Reuse via Reordering for Sparse Matrix-Vector Multiplication on FPGAs.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

HSCoNAS: Hardware-Software Co-Design of Efficient DNNs via Neural Architecture Search.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

ZeroBN: Learning Compact Neural Networks For Latency-Critical Edge Systems.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Energy-Efficient Parallel Real-Time Scheduling on Clustered Multi-Core.
IEEE Trans. Parallel Distributed Syst., 2020

Energy-Aware Offloading in Time-Sensitive Networks with Mobile Edge Computing.
CoRR, 2020

Joint Offloading and Resource Allocation for Time-Sensitive Multi-Access Edge Computing Network.
Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020

EdgeNAS: Discovering Efficient Neural Architectures for Edge Systems.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
Real-Time Scheduling of DAG Tasks with Arbitrary Deadlines.
ACM Trans. Design Autom. Electr. Syst., 2019

A process partitioning technique for constructing decentralized web service compositions.
Softw. Pract. Exp., 2019

CASS: Criticality-Aware Standby-Sparing for real-time systems.
J. Syst. Archit., 2019

Confidential Cooperative Communication with the Trust Degree of Jammer.
Entropy, 2019

ReLeTA: Reinforcement Learning for Thermal-Aware Task Allocation on Multicore.
CoRR, 2019

Knowledge Graph-Based Image Classification Refinement.
IEEE Access, 2019

Energy-Efficient Real-Time Scheduling of DAGs on Clustered Multi-Core Platforms.
Proceedings of the 25th IEEE Real-Time and Embedded Technology and Applications Symposium, 2019

Analyzing GEDF Scheduling for Parallel Real-Time Tasks with Arbitrary Deadlines.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Scheduling Analysis of Imprecise Mixed-Criticality Real-Time Tasks.
IEEE Trans. Computers, 2018

Utilization-Based Scheduling of Flexible Mixed-Criticality Real-Time Tasks.
IEEE Trans. Computers, 2018

Brain Tumor Segmention Based on Dilated Convolution Refine Networks.
Proceedings of the 16th IEEE International Conference on Software Engineering Research, 2018

2016
On the Improved Hard Real-Time Scheduling of Cyclo-Static Dataflow.
ACM Trans. Embed. Comput. Syst., 2016

Reconfigurable cache for real-time MPSoCs: Scheduling and implementation.
Microprocess. Microsystems, 2016

EDF-VD Scheduling of Mixed-Criticality Systems with Degraded Quality Guarantees.
Proceedings of the 2016 IEEE Real-Time Systems Symposium, 2016

Energy-Efficient Scheduling of Real-Time Tasks on Heterogeneous Multicores Using Task Splitting.
Proceedings of the 22nd IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2016

Exploiting resource-constrained parallelism in hard real-time streaming applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Energy-efficient mapping of real-time applications on heterogeneous MPSoCs using task replication.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

2015
Energy-efficient mapping of real-time streaming applications on cluster heterogeneous MPSoCs.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Improved hard real-time scheduling of CSDF-modeled streaming applications.
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015

2014
Automatic cache partitioning and time-triggered scheduling for real-time MPSoCs.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Abstract: Shared L2 Cache Management in Multicore Real-Time System.
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Resource optimization for CSDF-modeled streaming applications with latency constraints.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014


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