Dhruva R. Chakrabarti
Orcid: 0009-0008-4660-7584Affiliations:
- Hewlett Packard Enterprise Labs, Palo Alto, CA, USA
According to our database1,
Dhruva R. Chakrabarti
authored at least 31 papers
between 1995 and 2023.
Collaborative distances:
Collaborative distances:
Timeline
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Online presence:
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on labs.hpe.com
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on dl.acm.org
On csauthors.net:
Bibliography
2023
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
2017
Proceedings of the 31st International Symposium on Distributed Computing, 2017
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017
2016
Proceedings of the 2016 ACM SIGPLAN International Conference on Object-Oriented Programming, 2016
Proceedings of the Languages and Compilers for Parallel Computing, 2016
Proceedings of the 2016 ACM SIGPLAN International Symposium on Memory Management, Santa Barbara, CA, USA, June 14, 2016
2015
Procrastination Beats Prevention: Timely Sufficient Persistence for Efficient Crash Resilience.
Proceedings of the 18th International Conference on Extending Database Technology, 2015
2014
Proceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages & Applications, 2014
2013
Proceedings of the 5th USENIX Workshop on Hot Topics in Parallelism, 2013
2012
On a Technique for Transparently Empowering Classical Compiler Optimizations on Multithreaded Code.
ACM Trans. Program. Lang. Syst., 2012
2011
A technique for the effective and automatic reuse of classical compiler optimizations on multithreaded code.
Proceedings of the 38th ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 2011
Proceedings of the 2011 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '11, 2011
The runtime abort graph and its application to software transactional memory optimization.
Proceedings of the CGO 2011, 2011
2010
Compiler aided selective lock assignment for improving the performance of software transactional memory.
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010
Analysis on semantic transactional memory footprint for hardware transactional memory.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010
2009
Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2009
2006
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006
2004
Proceedings of the 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 2004
Proceedings of the 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September, 2004
2001
Int. J. Parallel Program., 2001
Proceedings of the 15th international conference on Supercomputing, 2001
2000
Compiler and Run-Time Support for Exploiting Regularity within Irregular Applications.
IEEE Trans. Parallel Distributed Syst., 2000
1999
Proceedings of the Languages and Compilers for Parallel Computing, 1999
A Novel Compilation Framework for Supporting Semi-Regular Distributions in Hybrid Applications.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999
1998
Evaluation of Compiler and Runtime Library Approaches for Supporting Parallel Regular Applications.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998
Proceedings of the 12th international conference on Supercomputing, 1998
Proceedings of the 5th International Conference On High Performance Computing, 1998
1996
An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
1995
An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995