Dhruva Acharyya

According to our database, Dhruva Acharyya authored at least 17 papers between 2003 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

HELP: A Hardware-Embedded Delay PUF.

Jim Aarestad, Philip Ortiz, Dhruva Acharyya, Jim Plusquellic

IEEE Des. Test, 2013

Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF.

Jim Aarestad, Jim Plusquellic, Dhruva Acharyya

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique.

Raj Chakraborty, Charles Lamech, Dhruva Acharyya, Jim Plusquellic

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2011

Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current.

Dhruva Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson

Proceedings of the 2011 IEEE International Test Conference, 2011

Measuring within-die spatial variation profile through power supply current measurements.

Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect.

Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal

Proceedings of the 48th Design Automation Conference, 2011

2010

Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad I_DDQ s.

Jim Aarestad, Dhruva Acharyya, Reza M. Rad, Jim Plusquellic

IEEE Trans. Inf. Forensics Secur., 2010

Leveraging existing power control circuits and power delivery architecture for variability measurement.

Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic

Proceedings of the 2011 IEEE International Test Conference, 2010

Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system.

Ryan Helinski, Dhruva Acharyya, Jim Plusquellic

Proceedings of the 47th Design Automation Conference, 2010

2009

Characterizing within-die variation from multiple supply port IDDQ measurements.

Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A physical unclonable function defined using power distribution system equivalent resistance variations.

Ryan Helinski, Dhruva Acharyya, Jim Plusquellic

Proceedings of the 46th Design Automation Conference, 2009

2007

Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.

Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Rigorous extraction of process variations for 65nm CMOS design.

Wei Zhao, Yu Cao, Frank Liu, Kanak Agarwal, Dhruva Acharyya, Sani R. Nassif, Kevin J. Nowka

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method.

Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel

IEEE Des. Test Comput., 2006

2005

Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements.

Dhruva Acharyya, Jim Plusquellic

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2003

Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids.

Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhruva Acharyya, Jim Plusquellic

J. Electron. Test., 2003

Impedance Profile of a Commercial Power Grid and Test System.

Dhruva Acharyya, Jim Plusquellic

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003