Dheemanth Nagaraj

According to our database, Dheemanth Nagaraj authored at least 3 papers between 2010 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

ScaleDeep: A Scalable Compute Architecture for Learning and Evaluating Deep Networks.

Swagath Venkataramani, Ashish Ranjan, Subarno Banerjee, Dipankar Das, Sasikanth Avancha, Ashok Jagannathan, Ajaya Durg, Dheemanth Nagaraj, Bharat Kaul, Pradeep Dubey, Anand Raghunathan

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2015

Intel® Xeon® Processor D: The First Xeon processor optimized for dense solutions.

Dheemanth Nagaraj, Chris Gianos

Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2010

Westmere-EX: A 20 thread server CPU.

Dheemanth Nagaraj, Sailesh Kottapalli

Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010