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Dharmendra Yadeo

Orcid: 0000-0002-7975-255X

According to our database1, Dharmendra Yadeo authored at least 3 papers between 2019 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A hybrid five-level inverter configuration with improved reliability and reduced number of components.
[BibTeX]
[DOI]
Sai Krishna Saketi
,
Pradyumn Chaturvedi
,
Dharmendra Yadeo
,
Dipesh Atkar
Int. J. Circuit Theory Appl., 2022

2019
Five Level Bidirectional Dual Active Bridge with Symmetrical Configuration.
[BibTeX]
[DOI]
Dharmendra Yadeo
,
Pradyumn Chaturvedi
,
H. M. Suryawanshi
,
Dipesh Atkar
,
Sai Krishna Saketi
Proceedings of the IECON 2019, 2019

A New Fault Tolerant Single Phase 5-Level Inverter Topology With Capacitor Voltage Balancing For Solid State Transformer.
[BibTeX]
[DOI]
Sai Krishna Saketi
,
Pradyumn Chaturvedi
,
Hiralal Murlidhar Suryawanshi
,
Dharmendra Yadeo
,
Dipesh Atkar
Proceedings of the IECON 2019, 2019


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