Dharmaray Nedalgi

According to our database, Dharmaray Nedalgi authored at least 7 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of seven.
• Erdős number of seven.

2024

2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues.

Dharmaray Nedalgi, Saroja V. Siddamal, S. S. Kerur

Integr., 2024

2023

Supply Noise and Peak Current Reduction in High-Speed Output Drivers.

Dharmaray Nedalgi, Lavanya M. N, Saroja V. Siddamal

Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022

Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability.

Dharmaray Nedalgi, Saroja V. Siddamal

J. Circuits Syst. Comput., 2022

Differential receiver with 2 × VDD input signals using 1 × VDD devices.

Dharmaray Nedalgi, Saroja V. Siddamal

Integr., 2022

2021

High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone.

Dharmaray Nedalgi, Saroja V. Siddamal

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

$2 \times \text{VDD}$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability.

Dharmaray Nedalgi, Saroja V. Siddamal

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer.

Dharmaray Nedalgi, Saroja V. Siddamal

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021