Dhananjaya Wijerathne

According to our database, Dhananjaya Wijerathne authored at least 13 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications.

Vishnu P. Nambiar, Y. S. Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Z. Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, A. T. Do

Proceedings of the 21st International SoC Design Conference, 2024

PACE: A Scalable and Energy Efficient CGRA in a RISC-V SoC for Edge Computing Applications.

Vishnu P. Nambiar, Yi Sheng Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Zhaoying Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, Anh Tuan Do

Proceedings of the 36th IEEE Hot Chips Symposium, 2024

ZeD: A Generalized Accelerator for Variably Sparse Matrix Computations in ML.

Pranav Dangi, Zhenyu Bai, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra

Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023

Accelerating Edge AI with Morpher: An Integrated Design, Compilation and Simulation Framework for CGRAs.

Dhananjaya Wijerathne, Zhaoying Li, Tulika Mitra

CoRR, 2023

FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow.

Thilini Kaushalya Bandara, Dan Wu, Rohan Juneja, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

HiMap: Fast and Scalable High-Quality Mapping on CGRA via Hierarchical Abstraction.

Dhananjaya Wijerathne, Zhaoying Li, Anuj Pathania, Tulika Mitra, Lothar Thiele

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ChordMap: Automated Mapping of Streaming Applications Onto CGRA.

Zhaoying Li, Dhananjaya Wijerathne, Xianzhang Chen, Anuj Pathania, Tulika Mitra

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Power-Performance Characterization of TinyML Systems.

Yujie Zhang, Dhananjaya Wijerathne, Zhaoying Li, Tulika Mitra

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

LISA: Graph Neural Network based Portable Mapping on Spatial Accelerators.

Zhaoying Li, Dan Wu, Dhananjaya Wijerathne, Tulika Mitra

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRA.

Dhananjaya Wijerathne, Zhaoying Li, Thilini Kaushalya Bandara, Tulika Mitra

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

REVAMP: a systematic framework for heterogeneous CGRA realization.

Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh

Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022

2019

CASCADE: High Throughput Data Streaming via Decoupled Access-Execute CGRA.

Dhananjaya Wijerathne, Zhaoying Li, Manupa Karunarathne, Anuj Pathania, Tulika Mitra

ACM Trans. Embed. Comput. Syst., 2019

4D-CGRA: Introducing Branch Dimension to Spatio-Temporal Application Mapping on CGRAs.

Manupa Karunaratne, Dhananjaya Wijerathne, Tulika Mitra, Li-Shiuan Peh

Proceedings of the International Conference on Computer-Aided Design, 2019