Devender Pal Singh
Orcid: 0000-0001-8980-0896
According to our database1,
Devender Pal Singh
authored at least 4 papers
between 2021 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2021
2022
2023
2024
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Bibliography
2024
Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET.
Microelectron. J., 2024
2023
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2023
2022
Performance Analysis of Junctionless and Inversion Mode Trigate SOI FinFET at 20nm Gate Length.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021