Devarshi Mrinal Das

Orcid: 0000-0002-8092-0979

Affiliations:
  • Indian Institute of Technology (IIT) Ropar, Department of Electrical Engineering, Rupnagar, India
  • Indian Institute of Technology (IIT) Bombay, Department of Electrical Engineering, Mumbai, India


According to our database1, Devarshi Mrinal Das authored at least 39 papers between 2014 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2025
A low-power common-mode insensitive rail-to-rail dynamic comparator for ADCs.
Integr., 2025

2024
Design and Analysis of 3D Integrated Folded Ferro-Capacitive Crossbar Array (FC²A) for Brain-Inspired Computing System.
IEEE J. Emerg. Sel. Topics Circuits Syst., September, 2024

Circuit implementation of on-chip trainable spiking neural network using CMOS based memristive STDP synapses and LIF neurons.
Integr., March, 2024

Finding a Promising Oxide Material for Resistive Random Access Memory with Graphene Electrode.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

A Pulse Oximeter and a Controller Designed for Automatic Regulation of Oxygen Concentrators.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Modeling and Comparing the Impact of Resistive and Capacitive Crossbar Associated Parasitics of Neuromorphic Circuits.
Proceedings of the 31st International Conference on Mixed Design of Integrated Circuits and System , 2024

A 0.006 mm<sup>2</sup> Low Input Capacitance Low Power Fully Differential Neural Amplifier.
Proceedings of the 31st International Conference on Mixed Design of Integrated Circuits and System , 2024

A 66 $\mu \mathrm{W}$ Asynchronous Time-Domain Bulk-Tuned Offset Cancellation Circuit for High-Precision Dynamic Comparator.
Proceedings of the 31st International Conference on Mixed Design of Integrated Circuits and System , 2024

A 66dBΩ 5 GHz and 44.88 √Hz/(pA·pW) Inductorless TIA in 65 nm CMOS.
Proceedings of the 31st International Conference on Mixed Design of Integrated Circuits and System , 2024

A Novel Charge Neutral, Programmable, Wireless Brain Stimulation System for Rat Experiments.
Proceedings of the 8th International Conference on Biomedical Engineering and Applications, 2024

2023
A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks.
Circuits Syst. Signal Process., November, 2023

Optimization of Slew Mitigation Capacitor in Passive Charge Compensation-Based Delta-Sigma Modulator.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

Full CMOS Circuit for Brain-Inspired Associative Memory With On-Chip Trainable Memristive STDP Synapse.
IEEE Trans. Very Large Scale Integr. Syst., 2023

A Low Power Differential Delay Cell without Cross-Coupled Latch for Ring VCO.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

Analysing Mismatch effect of CMOS Neurons in Spiking Neural Network with Winner-take-all Mechanism.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
CMOS Circuit Implementation of Spiking Neural Network for Pattern Recognition Using On-chip Unsupervised STDP Learning.
CoRR, 2022

A Low-Overhead PUF Based Hardware Security Technique to Prevent Scan Chain Attacks for Industry-Standard DFT Architecture.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

6-bit 1-GS/s Partially Active Flash ADC with Comparator Offset Correction.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2021
Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing.
Proceedings of the 25th International Symposium on VLSI Design and Test, 2021

Full CMOS Implementation of Bidirectional Associative Memory Neural Network with Analog Memristive Synapse.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

Analysis of Parasitics on CMOS based Memristor Crossbar Array for Neuromorphic Systems.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A low power 8 × 2<sup>7</sup>-1 PRBS generator using Exclusive-OR gate merged D flip-flops.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A CMOS based High Resolution All-Digital Temperature Sensor with Low Power Supply Sensitivity.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

A Robust Training Signal Generator for Trainable Memristive Digital to Analog Converter.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Python-LTspice Co-Simulation to Train Neural Networks with Memristive Synapses to Learn Logic Gate Operations.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

Design and Implementation of 0.23 nJ/bit Reference-Spur-Free FSK/OOK Transmitter at 400 MHz for Wearable Health Monitoring.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

2020
Adaptive analogue calibration technique to compensate electrode motion artefacts in biopotential recording.
IET Circuits Devices Syst., 2020

Noise-power-area optimised design procedure for OTAs with complementary input transistors for neural amplifiers.
IET Circuits Devices Syst., 2020

2019
Design and development of an Internet-of-Things enabled wearable ExG measuring system with a novel signal processing algorithm for electrocardiogram.
IET Circuits Devices Syst., 2019

2018
Bio-WiTel: A Low-Power Integrated Wireless Telemetry System for Healthcare Applications in 401-406 MHz Band of MedRadio Spectrum.
IEEE J. Biomed. Health Informatics, 2018

A pulse oximeter system, <i>OxiSense</i>, with embedded signal processing using an ultra-low power ASIC designed for testability.
Microelectron. J., 2018

2017
LNA-LO Co-design Considerations for Low Intermediate Frequency Receivers in 401-406 MHz MedRadio Spectrum for Healthcare Applications.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A noise-power-area optimized novel programmable gain and bandwidth instrumentation amplifier for biomedical applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A novel low-noise fully differential CMOS instrumentation amplifier with 1.88 noise efficiency factor for biomedical and sensor applications.
Microelectron. J., 2016

Design and measurement techniques for a low noise amplifier in a receiver chain for MedRadio spectrum of 401-406 MHz frequency band.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technology.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

SAW resonator oscillator based injection locked OOK transmitter for MedRadio spectrum.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2014
Design considerations for high-CMRR low-power current mode instrumentation amplifier for biomedicai data acquisition systems.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014


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