Derong Liu

According to our database, Derong Liu authored at least 14 papers between 2015 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.

Derong Liu, Bei Yu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Device Layer-Aware Analytical Placement for Analog Circuits.

Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan

Proceedings of the 2019 International Symposium on Physical Design, 2019

Exploiting Wavelength Division Multiplexing for Optical Logic Synthesis.

Zheng Zhao, Derong Liu, Zhoufeng Ying, Biying Xu, Chenghao Feng, Ray T. Chen, David Z. Pan

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Hardware-software co-design of slimmed optical neural networks.

Zheng Zhao, Derong Liu, Meng Li, Zhoufeng Ying, Lu Zhang, Biying Xu, Bei Yu, Ray T. Chen, David Z. Pan

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations.

Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees.

Charles J. Alpert, Wing-Kai Chow, Kwangsoo Han, Andrew B. Kahng, Zhuo Li, Derong Liu, Sriram Venkatesh

Proceedings of the 2018 International Symposium on Physical Design, 2018

OPERON: optical-electrical power-efficient route synthesis for on-chip signals.

Derong Liu, Zheng Zhao, Zheng Wang, Zhoufeng Ying, Ray T. Chen, David Z. Pan

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Incremental Layer Assignment for Timing Optimization.

Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan

ACM Trans. Design Autom. Electr. Syst., 2017

Incremental Layer Assignment Driven by an External Signoff Timing Engine.

Vinicius S. Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, José Luís Almada Güntzel, Luiz C. V. dos Santos

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups.

Derong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

OSFA: A New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions.

Subhendu Roy, Derong Liu, Jagmohan Singh, Junhyung Um, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Incremental layer assignment for critical path timing.

Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

TILA: Timing-Driven Incremental Layer Assignment.

Bei Yu, Derong Liu, Salim Chowdhury, David Z. Pan

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

OSFA: a new paradigm of gate-sizing for power/performance optimizations under multiple operating conditions.

Subhendu Roy, Derong Liu, Junhyung Um, David Z. Pan

Proceedings of the 52nd Annual Design Automation Conference, 2015