Derek Wright

According to our database1, Derek Wright authored at least 9 papers between 2003 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2021
Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Ultra Low-power, Low-energy Static Single-phase Clocked Flip-flop.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

2019
Hybrid Latch-Type Offset Tolerant Sense Amplifier for Low-Voltage SRAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
Sense amplifier offset characterisation and test implications for low-voltage SRAMs in 65 nm.
Proceedings of the 23rd IEEE European Test Symposium, 2018

2009
A Low-Power Ternary CAM With Positive-Feedback Match-Line Sense Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2006
Design techniques and test methodology for low-power TCAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Match Line Sense Amplifiers with Positive Feedback for Low-Power Content Addressable Memories.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005
Co-Scheduling of Computation and Data on Computer Clusters.
Proceedings of the 17th International Conference on Scientific and Statistical Database Management, 2005

2003
Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003


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