Deping Huang
According to our database1,
Deping Huang
authored at least 10 papers
between 2010 and 2016.
Collaborative distances:
Collaborative distances:
Timeline
2010
2011
2012
2013
2014
2015
2016
0
1
2
3
4
1
1
1
1
1
3
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2016
A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator.
IEEE Trans. Very Large Scale Integr. Syst., 2016
2015
Effect of OPAMP Input Offset on Continuous-Time ΔΣ Modulators With Current-Mode DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
2013
A radiation-hardened DLL with fine resolution and DCC for DDR2 memory interface in 0.13 μm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
A PVT-robust current-mode passive mixer with source-degenerated transconductance amplifier.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A Frequency Synthesizer With Optimally Coupled QVCO and Harmonic-Rejection SSBmixer for Multi-Standard Wireless Receiver.
IEEE J. Solid State Circuits, 2011
A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
A fractional-N frequency synthesizer for cellular and short range multi-standard wireless receiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010