Dennis Walter
According to our database1,
Dennis Walter
authored at least 33 papers
between 2005 and 2023.
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Bibliography
2023
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI.
Proceedings of the 20th International SoC Design Conference, 2023
A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI.
IEEE Trans. Biomed. Circuits Syst., 2022
ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.
CoRR, 2021
2020
Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020
2019
How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC.
Proceedings of the 49th European Solid-State Device Research Conference, 2019
2018
A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS.
IEEE J. Solid State Circuits, 2015
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015
2014
10.7 A 105GOPS 36mm<sup>2</sup> heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links.
Int. J. Embed. Real Time Commun. Syst., 2012
Guaranteeing functional safety: design for provability and computer-aided verification.
Auton. Robots, 2012
A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the 2011 International Symposium on System on Chip, 2011
2010
A formal verification environment for use in the certification of safety-related C-programs.
PhD thesis, 2010
Proceedings of the Computer Safety, 2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
2009
Proceedings of the FM 2009: Formal Methods, 2009
2008
Theor. Comput. Sci., 2008
Proceedings of the First Workshop on Certification of Safety-Critical Software Controlled Systems, 2008
Proceedings of the Software Engineering 2008, 2008
2005
Proceedings of the Algebra and Coalgebra in Computer Science: First International Conference, 2005