Dennis Michael Fischette

According to our database1, Dennis Michael Fischette authored at least 8 papers between 2008 and 2014.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
Wireline clocking and equalization.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013
Wireline transmitter and receiver design techniques.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors.
IEEE J. Solid State Circuits, 2012

2011
Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
An Embedded All-Digital Circuit to Measure PLL Response.
IEEE J. Solid State Circuits, 2010

A 45nm SOI-CMOS dual-PLL processor clock system for multi-protocol I/O.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
An on-chip all-digital measurement circuit to characterize phase-locked loop response in 45-nm SOI.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Session 17 - Clocking circuits.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008


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