Dennis J.-H. Huang

According to our database1, Dennis J.-H. Huang authored at least 16 papers between 1993 and 2023.

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Bibliography

2023
PROS 2.0: A Plug-In for Routability Optimization and Routed Wirelength Estimation Using Deep Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2020
PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2015
ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014
ePlace: Electrostatics Based Placement Using Nesterov's Method.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

1999
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement.
VLSI Design, 1999

1998
Multilevel circuit partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997
On implementation choices for iterative improvement partitioning algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Partitioning-based standard-cell global placement with an exact objective.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Faster minimization of linear wirelength for global placement.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Quadratic Placement Revisited.
Proceedings of the 34st Conference on Design Automation, 1997

1995
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Multi-way System Partitioning into a Single Type or Multiple Types of FPGAs.
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

When clusters meet partitions: new density-based methods for circuit decomposition.
Proceedings of the 1995 European Design and Test Conference, 1995

On the Bounded-Skew Clock and Steiner Routing Problems.
Proceedings of the 32st Conference on Design Automation, 1995

Quantified Suboptimality of VLSI Layout Heuristics.
Proceedings of the 32st Conference on Design Automation, 1995

1993
A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993


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