Denis Deschacht

According to our database, Denis Deschacht authored at least 15 papers between 1990 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

Crosstalk pulsewidth calculation.

Jean-Etienne Lorival, Denis Deschacht

Microelectron. J., 2010

2006

DSM interconnects: importance of inductance effects and corresponding range of length.

Denis Deschacht

IEEE Trans. Very Large Scale Integr. Syst., 2006

2005

Performances of Coupled Interconnect Lines: The Impact of Inductance and Routing Orientation.

Denis Deschacht, Alain Lopez

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004

Comparison between Different Data Buses Configurations.

Alain Lopez, Denis Deschacht

Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

2002

Impact of Low-K on Crosstalk.

Grégory Servel, Denis Deschacht, Françoise Saliou, Jean-Luc Mattei, Fabrice Huret

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2001

On-chip interconnections: impact of adjacent lines on timing.

Denis Deschacht, Grégory Servel

Proceedings of ASP-DAC 2001, 2001

2000

Theoretical limits for signal reflections due to inductance for on-chip interconnections.

Denis Deschacht, Grégory Servel, Fabrice Huret, Erick Paleczny, Patrick Kennis

Proceedings of the Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), 2000

On-chip crosstalk evaluation between adjacent interconnections.

Grégory Servel, Denis Deschacht

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

1999

Inductance effect for interconnection timing analysis in submicronic circuits.

Grégory Servel, L. B. Kenmei, Fabrice Huret, Erick Paleczny, Patrick Kennis, Denis Deschacht

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1996

Delay propagation effect in transistor gates.

Denis Deschacht, Christophe Dabrin, Daniel Auvergne

IEEE J. Solid State Circuits, 1996

1995

A new and accurate interconnection delay time evaluation in a general tree-type network.

Denis Deschacht, Christophe Dabrin

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993

Post-layout timing simulation of CMOS circuits.

Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1991

TVA: A timing verifier with analytic temporal modelling.

D. Navarro, A. Roy, Michel Robert, Denis Deschacht, Daniel Auvergne

Microprocessing and Microprogramming, 1991

Formal sizing rules of CMOS circuits.

Daniel Auvergne, Nadine Azémard, V. Bonzom, Denis Deschacht, Michel Robert

Proceedings of the conference on European design automation, 1991

1990

Path runner: an accurate and fast timing analyser.

Denis Deschacht, P. Pinede, Michel Robert, Daniel Auvergne

Proceedings of the European Design Automation Conference, 1990