Dengjie Wang
Orcid: 0000-0002-8918-4250
According to our database1,
Dengjie Wang
authored at least 6 papers
between 2017 and 2022.
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Collaborative distances:
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Bibliography
2022
A 56-Gbps PAM-4 Wireline Receiver With 4-Tap Direct DFE Employing Dynamic CML Comparators in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
2021
An 11.05 mW/Gbps Quad-Channel 1.25-10.3125 Gbps Serial Transceiver With a 2-Tap Adaptive DFE and a 3-Tap Transmit FFE in 40 nm CMOS.
IEEE Access, 2021
A 40 Gbps PAM-4 Receiver with 12-Tap Direct Decision Feedback Equalizer Employing 1.5-stage Slicers in 65-nm CMOS.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
2018
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
2017
Design of 56 Gb/s PAM4 wire-line receiver with ring VCO based CDR in a 65 nm CMOS technology.
Proceedings of the 12th IEEE International Conference on ASIC, 2017