Deng Luo

Orcid: 0000-0003-0475-8268

According to our database1, Deng Luo authored at least 14 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
A Compact 16-Channel Neural Signal Recorder with Wireless Power and Data Transmission.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

ECANodule: Accurate Pulmonary Nodule Detection and Segmentation with Efficient Channel Attention.
Proceedings of the International Joint Conference on Neural Networks, 2023

2022
SynopSet: Multiscale Visual Abstraction Set for Explanatory Analysis of DNA Nanotechnology Simulations.
CoRR, 2022

Design of a Multi-Mode Animal Behavior Analysis System with Dual-View Video and Wireless Bio-Potential Acquisition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Modeling in the Time of COVID-19: Statistical and Rule-based Mesoscale Models.
IEEE Trans. Vis. Comput. Graph., 2021

2020
Design of a Low Noise Bio-Potential Recorder With High Tolerance to Power-Line Interference Under 0.8 V Power Supply.
IEEE Trans. Biomed. Circuits Syst., 2020

A 0.6V 12-Bit Binary-Scaled Redundant SAR ADC with 83dB SFDR.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Design of a Flexible Wearable Smart sEMG Recorder Integrated Gradient Boosting Decision Tree Based Hand Gesture Recognition.
IEEE Trans. Biomed. Circuits Syst., 2019

A Low-Noise Chopper Amplifier Designed for Multi-Channel Neural Signal Acquisition.
IEEE J. Solid State Circuits, 2019

A 0.8V Chopper Amplifier with 600mVpp Tolerance to Power-Line Interference for Neural Signal Acquisition.
Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

2018
Design of A Low Noise Neural Recording Amplifier for Closed-loop Neuromodulation Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design of a 3.24μW, 39nV/√Hz chopper amplifier with 5.5Hz noise corner frequency for invasive neural signal acquisition.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
Design of a closed-loop, bi-directional brain-machine-interface integrated on-chip spike sorting.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2015
A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015


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