Deming Chen
Orcid: 0000-0002-3016-0270
According to our database1,
Deming Chen
authored at least 282 papers
between 2003 and 2024.
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Bibliography
2024
AutoAI2C: An Automated Hardware Generator for DNN Acceleration on Both FPGA and ASIC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2024
CHARM 2.0: Composing Heterogeneous Accelerators for Deep Learning on Versal ACAP Architecture.
ACM Trans. Reconfigurable Technol. Syst., September, 2024
PandoGen: Generating complete instances of future SARS-CoV-2 sequences using Deep Learning.
PLoS Comput. Biol., January, 2024
CoRR, 2024
On the Surprising Efficacy of Distillation as an Alternative to Pre-Training Small Models.
CoRR, 2024
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024
Proceedings of the Forty-first International Conference on Machine Learning, 2024
Proceedings of the IEEE International Conference on Communications, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
Invited Paper: Software/Hardware Co-design for LLM and Its Application for Design Verification.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
Proceedings of the 17th IEEE International Conference on Cloud Computing, 2024
S2TAR: Shared Secure Trusted Accelerators with Reconfiguration for Machine Learning in the Cloud.
Proceedings of the 17th IEEE International Conference on Cloud Computing, 2024
Proceedings of the 17th IEEE International Conference on Cloud Computing, 2024
2023
ACM Trans. Reconfigurable Technol. Syst., September, 2023
Found. Trends Priv. Secur., 2023
RackBlox: A Software-Defined Rack-Scale Storage System with Network-Storage Co-Design.
Proceedings of the 29th Symposium on Operating Systems Principles, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023
Proceedings of the Eleventh International Conference on Learning Representations, 2023
Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023
CHARM: Composing Heterogeneous AcceleRators for Matrix Multiply on Versal ACAP Architecture.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
ACM Trans. Reconfigurable Technol. Syst., 2022
ACM Trans. Reconfigurable Technol. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
ReAAP: A Reconfigurable and Algorithm-Oriented Array Processor With Compiler-Architecture Co-Design.
IEEE Trans. Computers, 2022
DML: Dynamic Partial Reconfiguration With Scalable Task Scheduling for Multi-Applications on FPGAs.
IEEE Trans. Computers, 2022
HiKonv: Maximizing the Throughput of Quantized Convolution With Novel Bit-wise Management and Computation.
CoRR, 2022
CoRR, 2022
AutoDistill: an End-to-End Framework to Explore and Distill Hardware-Efficient Language Models.
CoRR, 2022
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022
BoFL: bayesian optimized local training pace control for energy efficient federated learning.
Proceedings of the Middleware '22: 23rd International Middleware Conference, Quebec, QC, Canada, November 7, 2022
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
EDAML 2022 Invited Speaker 2: AI Algorithm and Accelerator Co-design for Computing on the Edge.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Qilin: Enabling Performance Analysis and Optimization of Shared-Virtual Memory Systems with FPGA Accelerators.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the International Conference on Field-Programmable Technology, 2022
ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
HiKonv: High Throughput Quantized Convolution With Novel Bit-wise Management and Computation.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Behavioral Synthesis for Hardware Security, 2022
2021
Learning-Based Simultaneous Detection and Characterization of Time Delay Attack in Cyber-Physical Systems.
IEEE Trans. Smart Grid, 2021
IEEE Trans. Parallel Distributed Syst., 2021
IEEE Trans. Computers, 2021
IEEE Trans. Computers, 2021
Improving the Generalization Ability of Deep Neural Networks for Cross-Domain Visual Recognition.
IEEE Trans. Cogn. Dev. Syst., 2021
Trans. Assoc. Comput. Linguistics, 2021
Large Graph Convolutional Network Training with GPU-Oriented Data Communication Architecture.
Proc. VLDB Endow., 2021
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign.
IEEE Des. Test, 2021
CoRR, 2021
Being-ahead: Benchmarking and Exploring Accelerators for Hardware-Efficient AI Deployment.
CoRR, 2021
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design.
CoRR, 2021
PyTorch-Direct: Enabling GPU Centric Data Access for Very Large Graph Neural Network Training with Irregular Accesses.
CoRR, 2021
HELLO: improved neural network architectures and methodologies for small variant calling.
BMC Bioinform., 2021
A Python-based High-Level Programming Flow for CPU-FPGA Heterogeneous Systems : (Invited Paper).
Proceedings of the IEEE/ACM Programming Environments for Heterogeneous Computing, 2021
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
Chimera: A Hybrid Machine Learning-Driven Multi-Objective Design Space Exploration Tool for FPGA High-Level Synthesis.
Proceedings of the Intelligent Data Engineering and Automated Learning - IDEAL 2021, 2021
Improved GPU Implementations of the Pair-HMM Forward Algorithm for DNA Sequence Alignment.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition.
Proceedings of the Formal Methods in Computer Aided Design, 2021
Extending HLS with High-Level Descriptive Language for Configurable Algorithm-Level Spatial Structure Design.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs.
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021
Software/Hardware Co-design for Multi-modal Multi-task Learning in Autonomous Systems.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems.
Proceedings of the Third Conference on Machine Learning and Systems, 2020
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020
Proceedings of the 40th IEEE International Conference on Distributed Computing Systems, 2020
DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN Accelerator.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
HybridDNN: A Framework for High-Performance Hybrid DNN Accelerator Design and Implementation.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 10th Conference on Innovative Data Systems Research, 2020
Thanos: High-Performance CPU-GPU Based Balanced Graph Partitioning Using Cross-Decomposition.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
ACM Trans. Reconfigurable Technol. Syst., 2019
A Hardware-Efficient Block Matching Algorithm and Its Hardware Design for Variable Block Size Motion Estimation in Ultra-High-Definition Video Encoding.
ACM Trans. Design Autom. Electr. Syst., 2019
Hybrid Quick Error Detection: Validation and Debug of SoCs Through High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019
IEEE Trans. Computers, 2019
CoRR, 2019
Analysis and Modeling of Collaborative Execution Strategies for Heterogeneous CPU-FPGA Architectures.
Proceedings of the 2019 ACM/SPEC International Conference on Performance Engineering, 2019
Proceedings of the 2019 IEEE International Workshop on Signal Processing Systems, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the IEEE International Conference on Acoustics, 2019
Proceedings of the 2019 IEEE High Performance Extreme Computing Conference, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Implementing neural machine translation with bi-directional GRU and attention mechanism on FPGAs using HLS.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
Proceedings of the 22nd International Conference on Artificial Intelligence and Statistics, 2019
2018
ACM Trans. Reconfigurable Technol. Syst., 2018
C-Mine: Data Mining of Logic Common Cases for Improved Timing Error Resilience with Energy Efficiency.
ACM Trans. Design Autom. Electr. Syst., 2018
Compact Modeling to Device- and Circuit-Level Evaluation of Flexible TMD Field-Effect Transistors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Application-Transparent Near-Memory Processing Architecture with Memory Channel Network.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
Improved ASR for Under-resourced Languages through Multi-task Learning with Acoustic Landmarks.
Proceedings of the 19th Annual Conference of the International Speech Communication Association, 2018
DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAs.
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Design Flow of Accelerating Hybrid Extremely Low Bit-Width Neural Network in Embedded FPGA.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018
Proceedings of the Computer Vision - ECCV 2018 Workshops, 2018
Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices.
Proceedings of the 20th System Level Interconnect Prediction Workshop, 2018
CSRNet: Dilated Convolutional Neural Networks for Understanding the Highly Congested Scenes.
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018
2017
Heterogeneous Computing Meets Near-Memory Acceleration and High-Level Synthesis in the Post-Moore Era.
IEEE Micro, 2017
Integr., 2017
Acoustic Landmarks Contain More Information About the Phone String than Other Frames.
CoRR, 2017
Proceedings of the 8th ACM/SPEC on International Conference on Performance Engineering, 2017
Using Approximated Auditory Roughness as a Pre-Filtering Feature for Human Screaming and Affective Speech AED.
Proceedings of the 18th Annual Conference of the International Speech Communication Association, 2017
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
High-performance video content recognition with long-term recurrent convolutional network for FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017
Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration.
Proceedings of the 54th Annual Design Automation Conference, 2017
ASP-DAC 2017 keynote speech I: In memory of Edward J. McCluskey: The next wave of pioneering innovations.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017
2016
Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2016
FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow.
IEEE Trans. Very Large Scale Integr. Syst., 2016
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
FCUDA-HB: Hierarchical and Scalable Bus Architecture Generation on FPGAs With the FCUDA Flow.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
IEEE Trans. Computers, 2016
Platform choices and design demands for IoT platforms: cost, power, and performance tradeoffs.
IET Cyper-Phys. Syst.: Theory & Appl., 2016
Bioinform., 2016
SoC, NoC and Hierarchical Bus Implementations of Applications on FPGAs Using the FCUDA Flow.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Parallel code-specific CPU simulation with dynamic phase convergence modeling for HW/SW co-design.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Automated Verification Code Generation in HLS Using Software Execution Traces (Abstract Only).
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
FCUDA-SoC: Platform Integration for Field-Programmable SoC with the CUDA-to-FPGA Compiler.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016
Real-time system-level implementation of a telepresence robot using an embedded GPU platform.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation.
Proceedings of the 53rd Annual Design Automation Conference, 2016
Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Flexible transition metal dichalcogenide field-effect transistors: A circuit-level simulation study of delay and power under bending, process variation, and scaling.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Parallel Distributed Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
IPSJ Trans. Syst. LSI Des. Methodol., 2015
CSL: Coordinated and scalable logic synthesis techniques for effective NBTI reduction.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015
A Polyhedral-based SystemC Modeling and Generation Framework for Effective Low-power Design Space Exploration.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles.
Proceedings of the 52nd Annual Design Automation Conference, 2015
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Hybrid circuit-switched network for on-chip communication in large-scale chip-multiprocessors.
J. Parallel Distributed Comput., 2014
BLESS: Bloom filter-based error correction solution for high-throughput sequencing reads.
Bioinform., 2014
Proceedings of the IEEE Eighth International Conference on Software Security and Reliability, 2014
Proceedings of the 2014 IEEE 20th International Conference on Embedded and Real-Time Computing Systems and Applications, 2014
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014
Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014
Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
ClusRed: Clustering and Network Reduction Based Probabilistic Optimal Power Flow Analysis for Large-Scale Smart Grids.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014
Fast large-scale optimal power flow analysis for smart grid through network reduction.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware design.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
ACM Trans. Design Autom. Electr. Syst., 2013
ACM Trans. Embed. Comput. Syst., 2013
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013
Schottky-barrier-type Graphene Nano-Ribbon Field-Effect Transistors: A study on compact modeling, process variation, and circuit performance.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Improving high level synthesis optimization opportunity through polyhedral transformations.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation.
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
Analysis of Digital Circuit Dynamic Behavior With Timed Ternary Decision Diagrams for Better-Than-Worst-Case Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
J. Electr. Comput. Eng., 2012
Int. J. Reconfigurable Comput., 2012
Improving broadcast efficiency in wireless sensor network time synchronization protocols.
Proceedings of the International Workshop on System Level Interconnect Prediction, 2012
CCP: common case promotion for improved timing error resilience with energy efficiency.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
An Accurate GPU Performance Model for Effective Control Flow Divergence Optimization.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012
Real-time implementation and performance optimization of 3D sound localization on GPUs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Proceedings of the 2011 International Workshop on System Level Interconnect Prediction, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
High level synthesis of stereo matching: Productivity, performance, and software constraints.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Int. J. Reconfigurable Comput., 2010
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
Proceedings of the Springer Handbook of Automation, 2009
A Fast Digital Predistortion Algorithm for Radio-Frequency Power Amplifier Linearization With Loop Delay Compensation.
IEEE J. Sel. Top. Signal Process., 2009
An Optimal Resource Binding Algorithm with Inter-Transition Switching Activities for Low Power.
J. Low Power Electron., 2009
Int. J. Parallel Program., 2009
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
Workload adaptive shared memory multicore processors with reconfigurable interconnects.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Proceedings of the 23rd international conference on Supercomputing, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation.
Proceedings of the 46th Design Automation Conference, 2009
FastYield: variation-aware, layout-driven simultaneous binding and module selection for performance yield optimization.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.
ACM Trans. Design Autom. Electr. Syst., 2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor.
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Efficient ASIP design for configurable processors with fine-grained resource sharing.
Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Performance and power evaluation of a 3D CMOS/nanomaterial reconfigurable architecture.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Timing constraint-driven technology mapping for FPGAs considering false paths and multi-clock domains.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
ACM Trans. Design Autom. Electr. Syst., 2006
Proceedings of the 43rd Design Automation Conference, 2006
A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 43rd Design Automation Conference, 2006
2005
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
Proceedings of the 2005 International Symposium on Autonomous Decentralized Systems, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003