Delong Shang
Orcid: 0009-0000-6674-2347
According to our database1,
Delong Shang
authored at least 59 papers
between 2000 and 2025.
Collaborative distances:
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Bibliography
2025
SRRT: An Ultra-Low-Power Unidirectional Single-Wire Inter-Chip Communication for IoT.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025
2024
A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
Differentiable architecture search with multi-dimensional attention for spiking neural networks.
Neurocomputing, 2024
A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems.
IEEE Access, 2024
A 409mV, Sub-10nW Power-on Reset Circuit Using Adaptive Accuracy Adjustment for Low Voltage Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Multiscale Residual Network with Dynamic Depthwise Convolution for Multi-label 12-Lead ECG Classification.
Proceedings of the International Joint Conference on Neural Networks, 2024
Design of High-Performance while Energy-Efficient Microprocessor with Novel Asynchronous Techniques: (PhD Forum Paper).
Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024
2023
An exponential function accelerator with radix-16 algorithm for spiking neural networks.
IEICE Electron. Express, 2023
HPSAP: A High-Performance and Synthesizable Asynchronous Pipeline With Quasi-2phase Conversion Method.
IEEE Access, 2023
IEEE Access, 2023
AMA-Det: Enhancing Shared Head of One-Stage Object Detection With Adaptation, Merging, and Alignment.
IEEE Access, 2023
2022
IEICE Electron. Express, 2022
2021
IEICE Trans. Inf. Syst., 2021
Proceedings of the ICCCV 2021: 4th International Conference on Control and Computer Vision, Macau, SAR, China, August 13, 2021
2018
Proceedings of the 15th International Conference on Synthesis, 2018
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018
2016
Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016
2015
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015
2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Computers, 2013
Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
High-order reconfigurable FIR filter design based on statistical analysis of CSD coefficients.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013
2012
IET Comput. Digit. Tech., 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
ACM J. Emerg. Technol. Comput. Syst., 2011
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011
2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Fine-grain stochastic modelling of dynamic power management policies and analysis of their power - latency tradeoffs.
IET Softw., 2009
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
IET Comput. Digit. Tech., 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007
2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006
2005
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
2004
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 2004 Design, 2004
2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001
2000
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000