Deliang Fan
Orcid: 0000-0002-7989-6297
According to our database1,
Deliang Fan
authored at least 176 papers
between 2013 and 2024.
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., August, 2024
IEEE J. Solid State Circuits, July, 2024
IEEE Trans. Neural Networks Learn. Syst., March, 2024
Guest Editorial IEEE Transactions on Emerging Topics in Special Section on Emerging In-Memory Computing Architectures and Applications.
IEEE Trans. Emerg. Top. Comput., 2024
SafeguardGS: 3D Gaussian Primitive Pruning While Avoiding Catastrophic Scene Destruction.
CoRR, 2024
DeepShuffle: A Lightweight Defense Framework against Adversarial Fault Injection Attacks on Deep Neural Networks in Multi-Tenant Cloud-FPGA.
Proceedings of the IEEE Symposium on Security and Privacy, 2024
Improving the Efficiency of In-Memory-Computing Macro with a Hybrid Analog-Digital Computing Mode for Lossless Neural Network Inference.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Efficient Memory Integration: MRAM-SRAM Hybrid Accelerator for Sparse On-Device Learning.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
Hyb-Learn: A Framework for On-Device Self-Supervised Continual Learning with Hybrid RRAM/SRAM Memory.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024
SP-IMC: A Sparsity Aware In-Memory-Computing Macro in 28nm CMOS with Configurable Sparse Representation for Highly Sparse DNN Workloads.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
Proceedings of the Thirty-Eighth AAAI Conference on Artificial Intelligence, 2024
2023
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Efficient Self-supervised Continual Learning with Progressive Task-correlated Layer Freezing.
CoRR, 2023
Slimmed Asymmetrical Contrastive Learning and Cross Distillation for Lightweight Model Training.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023
Accelerating Low Bit-width Neural Networks at the Edge, PIM or FPGA: A Comparative Study.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
DSPIMM: A Fully Digital SParse In-Memory Matrix Vector Multiplier for Communication Applications.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
ACM Trans. Design Autom. Electr. Syst., 2022
IEEE Trans. Neural Networks Learn. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration.
IEEE Trans. Computers, 2022
IEEE Trans. Pattern Anal. Mach. Intell., 2022
IEEE Micro, 2022
IEEE Des. Test, 2022
APA-Scan: detection and visualization of 3′-UTR alternative polyadenylation with RNA-seq and 3′-end-seq data.
BMC Bioinform., 2022
DeepSteal: Advanced Model Extractions Leveraging Efficient Weight Stealing in Memories.
Proceedings of the 43rd IEEE Symposium on Security and Privacy, 2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the Tenth International Conference on Learning Representations, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
XMA: a crossbar-aware multi-task adaption framework via shift-based mask learning method.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022
DA<sup>3</sup>: Dynamic Additive Attention Adaption for Memory-Efficient On-Device Multi-Domain Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022
ResSFL: A Resistance Transfer Framework for Defending Model Inversion Attack in Split Federated Learning.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022
XBM: A Crossbar Column-wise Binary Mask Learning Method for Efficient Multiple Task Adaption.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022
Proceedings of the Thirty-Sixth AAAI Conference on Artificial Intelligence, 2022
2021
Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Non-Volatile Approximate Arithmetic Circuits Using Scalable Hybrid Spin-CMOS Majority Gates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Reducing SRAM Reading Power With Column Data Segment and Weights Correlation Enhancement for CNN Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
ACM J. Emerg. Technol. Comput. Syst., 2021
RA-BNN: Constructing Robust & Accurate Binary Neural Network to Simultaneously Defend Adversarial Bit-Flip Attack and Improve Accuracy.
CoRR, 2021
Self-supervised Novelty Detection for Continual Learning: A Gradient-Based Approach Boosted by Binary Classification.
Proceedings of the Continual Semi-Supervised Learning - First International Workshop, 2021
Deep-Dup: An Adversarial Weight Duplication Attack Framework to Crush Deep Neural Network in Multi-Tenant FPGA.
Proceedings of the 30th USENIX Security Symposium, 2021
MetaGater: Fast Learning of Conditional Channel Gated Networks via Federated Meta-Learning.
Proceedings of the IEEE 18th International Conference on Mobile Ad Hoc and Smart Systems, 2021
Characterization and Mitigation of Relaxation Effects on Multi-level RRAM based In-Memory Computing.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
NeurObfuscator: A Full-stack Obfuscation Tool to Mitigate Neural Architecture Stealing.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021
Processing-in-Memory Acceleration of MAC-based Applications Using Residue Number System: A Comparative Study.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Leveraging Noise and Aggressive Quantization of In-Memory Computing for Robust DNN Hardware Against Adversarial Input and Weight Attacks.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Handling Stuck-at-Fault Defects Using Matrix Transformation for Robust Inference of DNNs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
IEEE Trans. Computers, 2020
Sparse BD-Net: A Multiplication-less DNN with Sparse Binarized Depth-wise Separable Convolution.
ACM J. Emerg. Technol. Comput. Syst., 2020
CoRR, 2020
CCF Trans. High Perform. Comput., 2020
Network-based multi-task learning models for biomarker selection and cancer outcome prediction.
Bioinform., 2020
DeepHammer: Depleting the Intelligence of Deep Neural Networks through Targeted Chain of Bit Flips.
Proceedings of the 29th USENIX Security Symposium, 2020
Processing-in-Memory Accelerator for Dynamic Neural Network with Run-Time Tuning of Accuracy, Power and Latency.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
Redundant Neurons and Shared Redundant Synapses for Robust Memristor-based DNNs with Reduced Overhead.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Robust Sparse Regularization: Defending Adversarial Attacks Via Regularized Sparse Network.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020
Representable Matrices: Enabling High Accuracy Analog Computation for Inference of DNNs using Memristors.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
A Flexible Processing-in-Memory Accelerator for Dynamic Channel-Adaptive Deep Neural Networks.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
Harmonious Coexistence of Structured Weight Pruning and Ternarization for Deep Neural Networks.
Proceedings of the Thirty-Fourth AAAI Conference on Artificial Intelligence, 2020
2019
Robust Sparse Regularization: Simultaneously Optimizing Neural Network Robustness and Compactness.
CoRR, 2019
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Efficiency, and Power-Intermittency Resilience.
CoRR, 2019
CoRR, 2019
Optimize Deep Convolutional Neural Network with Ternarized Weights and High Accuracy.
Proceedings of the IEEE Winter Conference on Applications of Computer Vision, 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
Defense-Net: Defend Against a Wide Range of Adversarial Attacks through Adversarial Detector.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Processing-In-Memory Acceleration of Convolutional Neural Networks for Energy-Effciency, and Power-Intermittency Resilience.
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019
ReDRAM: A Reconfigurable Processing-in-DRAM Platform for Accelerating Bulk Bit-Wise Operations.
Proceedings of the International Conference on Computer-Aided Design, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the Device Research Conference, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAM.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
Parametric Noise Injection: Trainable Randomness to Improve Deep Neural Network Robustness Against Adversarial Attack.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019
Simultaneously Optimizing Weight and Quantizer of Ternary Neural Network Using Truncated Gaussian Approximation.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
ParaPIM: a parallel processing-in-memory accelerator for binary-weight deep neural networks.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
IEEE Trans. Multi Scale Comput. Syst., 2018
Stochastic-Based Synapse and Soft-Limiting Neuron with Spintronic Devices for Low Power and Robust Artificial Neural Networks.
IEEE Trans. Multi Scale Comput. Syst., 2018
Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
ACM J. Emerg. Technol. Comput. Syst., 2018
Defend Deep Neural Networks Against Adversarial Examples via Fixed andDynamic Quantized Activation Functions.
CoRR, 2018
CoRR, 2018
Proceedings of the 2018 IEEE Winter Conference on Applications of Computer Vision, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
A Fully Onchip Binarized Convolutional Neural Network FPGA Impelmentation with Accurate Inference.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial Networks.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Leveraging Spintronic Devices for Efficient Approximate Logic and Stochastic Neural Networks.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network accelerator.
Proceedings of the 55th Annual Design Automation Conference, 2018
PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computation.
Proceedings of the 55th Annual Design Automation Conference, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
IMCE: Energy-efficient bit-wise in-memory convolution engine for deep neural network.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
IEEE Trans. Emerg. Top. Comput., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
Survey of STT-MRAM Cell Design Strategies: Taxonomy and Sense Amplifier Tradeoffs for Resiliency.
ACM J. Emerg. Technol. Comput. Syst., 2017
Current Induced Dynamics of Multiple Skyrmions with Domain Wall Pair and Skyrmion-based Majority Gate Design.
CoRR, 2017
IMC: energy-efficient in-memory convolver for accelerating binarized deep neural network.
Proceedings of the Neuromorphic Computing Symposium, 2017
High performance and energy-efficient in-memory computing architecture based on SOT-MRAM.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Leveraging spintronic devices for ultra-low power in-memory computing: Logic and neural network.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
RIMPA: A New Reconfigurable Dual-Mode In-Memory Processing Architecture with Spin Hall Effect-Driven Domain Wall Motion Device.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Composite spintronic accuracy-configurable adder for low power Digital Signal Processing.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Exploring STT-MRAM Based In-Memory Computing Paradigm with Application of Image Edge Extraction.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Energy Efficient In-Memory Binary Deep Neural Network Accelerator with Dual-Mode SOT-MRAM.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Design of accurate stochastic number generators with noisy emerging devices for stochastic computing.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
Leveraging Dual-Mode Magnetic Crossbar for Ultra-low Energy In-memory Data Encryption.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Energy Efficient In-Memory Computing Platform Based on 4-Terminal Spin Hall Effect-Driven Domain Wall Motion Devices.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
A tunable magnetic skyrmion neuron cluster for energy efficient artificial neural network.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Hierarchical Temporal Memory Based on Spin-Neurons and Resistive Memory for Energy-Efficient Brain-Inspired Computing.
IEEE Trans. Neural Networks Learn. Syst., 2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devices.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
A Low Power Current-Mode Flash ADC with Spin Hall Effect based Multi-Threshold Comparator.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
Prospects of efficient neural computing with arrays of magneto-metallic neurons and synapses.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
PhD thesis, 2015
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015
2014
STT-SNN: A Spin-Transfer-Torque Based Soft-Limiting Non-Linear Neuron for Low-Power Artificial Neural Networks.
CoRR, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
CoRR, 2013
CoRR, 2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
Beyond charge-based computation: Boolean and non-Boolean computing with spin torque devices.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Ultra low power associative computing with spin neurons and resistive crossbar memory.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013