Dejan Markovic

According to our database1, Dejan Markovic authored at least 130 papers between 1997 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
ScoreDec: A Phase-Preserving High-Fidelity Audio Codec with a Generalized Score-Based Diffusion Post-Filter.
Proceedings of the IEEE International Conference on Acoustics, 2024

Modeling and Driving Human Body Soundfields Through Acoustic Primitives.
Proceedings of the Computer Vision - ECCV 2024, 2024

2023
A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration.
IEEE J. Solid State Circuits, 2023

Sounding Bodies: Modeling 3D Spatial Sound of Humans Using Body Pose and Audio.
Proceedings of the Advances in Neural Information Processing Systems 36: Annual Conference on Neural Information Processing Systems 2023, 2023

Spatialization Quality Metric for Binaural Speech.
Proceedings of the 24th Annual Conference of the International Speech Communication Association, 2023

Audiodec: An Open-Source Streaming High-Fidelity Neural Audio Codec.
Proceedings of the IEEE International Conference on Acoustics, 2023

Nord: Non-Matching Reference Based Relative Depth Estimation from Binaural Speech.
Proceedings of the IEEE International Conference on Acoustics, 2023

2022
Towards a Leadless Wirelessly Controlled Intravenous Cardiac Pacemaker.
IEEE Trans. Biomed. Eng., 2022

Reconstructing the Dynamic Directivity of Unconstrained Speech.
CoRR, 2022

A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Implicit Neural Spatial Filtering for Multichannel Source Separation in the Waveform Domain.
Proceedings of the 23rd Annual Conference of the International Speech Communication Association, 2022

End-to-End Binaural Speech Synthesis.
Proceedings of the 23rd Annual Conference of the International Speech Communication Association, 2022

Audio-Visual Speech Codecs: Rethinking Audio-Visual Speech Enhancement by Re-Synthesis.
Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2022

2021
Introduction to the Special Issue on the 2020 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2021

A Multi-Domain Architectural Efficiency Metric.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

Neural Synthesis of Binaural Speech From Mono Audio.
Proceedings of the 9th International Conference on Learning Representations, 2021

Implicit HRTF Modeling Using Temporal Convolutional Networks.
Proceedings of the IEEE International Conference on Acoustics, 2021

2020
A Multi-Dimensional Analysis of a Novel Approach for Wireless Stimulation.
IEEE Trans. Biomed. Eng., 2020

Analysis and Design of a Robust, Low-Power, Inductively Coupled LSK Data Link.
IEEE J. Solid State Circuits, 2020

2019
A 0.338 cm<sup>3</sup>, Artifact-Free, 64-Contact Neuromodulation Platform for Simultaneous Stimulation and Sensing.
IEEE Trans. Biomed. Circuits Syst., 2019

Simultaneous Transmission of Up To 94-mW Self-Regulated Wireless Power and Up To 5-Mb/s Reverse Data Over a Single Pair of Coils.
IEEE J. Solid State Circuits, 2019

1ST-Order Microphone Array System for Large Area Sound Field Recording and Reconstruction: Discussion and Preliminary Results.
Proceedings of the 2019 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, 2019

Soundfield Reconstruction in Reverberant Environments Using Higher-order Microphones and Impulse Response Measurements.
Proceedings of the IEEE International Conference on Acoustics, 2019

2018
A 2.267-Gb/s, 93.7-pJ/bit Non-Binary LDPC Decoder With Logarithmic Quantization and Dual-Decoding Algorithm Scheme for Storage Applications.
IEEE J. Solid State Circuits, 2018

A 15.2-ENOB 5-kHz BW 4.5-µW Chopped CT ΔΣ-ADC for Artifact-Tolerant Neural Recording Front Ends.
IEEE J. Solid State Circuits, 2018

Self-Regulated Wireless Power and Simultaneous 5MB/S Reverse Data over One Pair of Coils.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 15.2-ENOB continuous-time ΔΣ ADC for a 200mVpp-linear-input-range neural recording front-end.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Weighted Least Squares Beam Shaping Technique for Sound Field Control.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

2017
The application/pdf Media Type.
RFC, March, 2017

DataFlow Supercomputing Essentials - Research, Development and Education
Computer Communications and Networks, Springer, ISBN: 978-3-319-66127-8, 2017

A Miniaturized 0.78-mW/cm2 Autonomous Thermoelectric Energy-Harvesting Platform for Biomedical Sensors.
IEEE Trans. Biomed. Circuits Syst., 2017

Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2017

A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction.
IEEE J. Solid State Circuits, 2017

An 80-mVpp Linear-Input Range, 1.6- $\text{G}\Omega $ Input Impedance, Low-Power Chopper Amplifier for Closed-Loop Neural Recording That Is Tolerant to 650-mVpp Common-Mode Interference.
IEEE J. Solid State Circuits, 2017

A High Dynamic-Range Neural Recording Chopper Amplifier for Simultaneous Neural Recording and Stimulation.
IEEE J. Solid State Circuits, 2017

A blind Adaptive Stimulation Artifact Rejection (ASAR) engine for closed-loop implantable neuromodulation systems.
Proceedings of the 8th International IEEE/EMBS Conference on Neural Engineering, 2017

22.7 An inductively-coupled wireless power-transfer system that is immune to distance and load variations.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

27.1 A 2.8µW 80mVpp-linear-input-range 1.6GΩ-input impedance bio-signal chopper amplifier tolerant to common-mode interference up to 650mVpp.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A true full-duplex 32-channel 0.135cm<sup>3</sup> neural interface.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

A 216 nW/channel DSP engine for triggering theta phase-locked brain stimulation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
3D Beam Tracing Based on Visibility Lookup for Interactive Acoustic Modeling.
IEEE Trans. Vis. Comput. Graph., 2016

Extraction of Acoustic Sources Through the Processing of Sound Field Maps in the Ray Space.
IEEE ACM Trans. Audio Speech Lang. Process., 2016

A Configurable 12-237 kS/s 12.8 mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals.
IEEE J. Solid State Circuits, 2016

Using a nonparametric technique to measure the cost efficiency of postal delivery branches.
Central Eur. J. Oper. Res., 2016

A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

An informed separation algorithm based on sound field mapping for speech recognition systems.
Proceedings of the IEEE International Workshop on Acoustic Signal Enhancement, 2016

ES2: Computing architectures paving the path to power efficiency.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

28.6 A ±50mV linear-input-range VCO-based neural-recording front-end with digital nonlinearity correction.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

5.5 A 2µW 40mVpp linear-input-range chopper- stabilized bio-signal amplifier with boosted input impedance of 300MΩ and electrode-offset filtering.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A linear operator for the computation of soundfield maps.
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Reconfigure your RTL with EFLX join the SoC revolution.
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016

2015
A Heterogeneous Reconfigurable Cell Array for MIMO Signal Processing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Building Conflict-Free FFT Schedules.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

A Simple Area-Efficient Ripple-Rejection Technique for Chopped Biosignal Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Multiview Soundfield Imaging in the Projective Ray Space.
IEEE ACM Trans. Audio Speech Lang. Process., 2015

A Multi-Granularity FPGA With Hierarchical Interconnects for Efficient and Flexible Mobile Computing.
IEEE J. Solid State Circuits, 2015

Wideband blind signal classification on a battery budget.
IEEE Commun. Mag., 2015

Resolution issues in soundfield imaging: A multiresolution approach to multiple source localization.
Proceedings of the 2015 IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, 2015

A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015

A 0.78mW/cm<sup>2</sup> autonomous thermoelectric energy-harvester for biomedical sensors.
Proceedings of the Symposium on VLSI Circuits, 2015

18.5 A configurable 12-to-237KS/s 12.8mW sparse-approximation engine for mobile ExG data aggregation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Energy-Efficient Processor for Blind Signal Classification in Cognitive Radio Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Estimation of Acoustic Reflection Coefficients Through Pseudospectrum Matching.
IEEE ACM Trans. Audio Speech Lang. Process., 2014

A Robust Geometric Approach to Room Compensation for Sound Field Rendering.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Square Computation on Embedded Systems.
IEEE Embed. Syst. Lett., 2014

A 500MHz blind classification processor for cognitive radios in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

A 13.1GOPS/mW 16-core processor for software-defined radios in 40nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2014

27.5 A multi-granularity FPGA with hierarchical interconnects for efficient and flexible mobile computing.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Logarithmic quantization scheme for reduced hardware cost and improved error floor in non-binary LDPC decoders.
Proceedings of the IEEE Global Communications Conference, 2014

A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

A geometrical approach to room compensation for sound field rendering applications.
Proceedings of the 22nd European Signal Processing Conference, 2014

Robust, reconfigurable, and power-efficient biosignal recording systems.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

Field-order based hardware cost analysis of non-binary LDPC decoders.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Elaborazione plenacustica nello spazio dei raggi : modellazione e analisi delle scene acustiche.
PhD thesis, 2013

Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Soundfield Imaging in the Ray Space.
IEEE ACM Trans. Audio Speech Lang. Process., 2013

A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering.
IEEE J. Solid State Circuits, 2013

Estimation of room dimensions from a single impulse response.
Proceedings of the IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, 2013

Deconvolution of plenacoustic images.
Proceedings of the IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, 2013

An area-efficient minimum-time FFT schedule using single-ported memory.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A single-precision compressive sensing signal reconstruction engine on FPGAs.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Spike Sorting: The First Step in Decoding the Brain: The first step in decoding the brain.
IEEE Signal Process. Mag., 2012

A 7.4-mW 200-MS/s Wideband Spectrum Sensing Digital Baseband Processor for Cognitive Radios.
IEEE J. Solid State Circuits, 2012

Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example.
IEEE J. Solid State Circuits, 2012

Digitally intensive receiver design: opportunities and challenges.
IEEE Des. Test, 2012

Universal architecture prototype for patient-centric medical environment.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Plenacoustic Imaging in the Ray Space.
Proceedings of the IWAENC 2012 - International Workshop on Acoustic Signal Enhancement, Proceedings, RWTH Aachen University, Germany, September 4th, 2012

Reflection Coefficient Estimation by Pseudospectrum Matching.
Proceedings of the IWAENC 2012 - International Workshop on Acoustic Signal Enhancement, Proceedings, RWTH Aachen University, Germany, September 4th, 2012

A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs).
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Challenges and directions of ultra low energy wireless sensor nodes for biosignal monitoring.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A room-compensated virtual surround system exploiting early reflections in a reverberant room.
Proceedings of the 20th European Signal Processing Conference, 2012

ΣΔ modulators for low-power digitally intensive radio transmitters.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
A Wideband Spectrum-Sensing Processor With Adaptive Detection Threshold and Sensing Time.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011


Demonstration of Integrated Micro-Electro-Mechanical Relay Circuits for VLSI Applications.
IEEE J. Solid State Circuits, 2011

A 130- μ W, 64-Channel Neural Spike-Sorting DSP Chip.
IEEE J. Solid State Circuits, 2011

Energy-Efficient Retiming and Scheduling of Datapath-Dominant Digital Systems.
J. Low Power Electron., 2011

Analysis of STT-RAM cell design with multiple MTJs per access.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Scalability and design-space analysis of a 1T-1MTJ memory cell.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Effects of quantization on neural spike sorting.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A Hardware-Efficient VLSI Architecture for Hybrid Sphere-MCMC Detection.
Proceedings of the Global Communications Conference, 2011

An Energy-Efficient VLSI Architecture for Cognitive Radio Wideband Spectrum Sensing.
Proceedings of the Global Communications Conference, 2011

Compressive Sensing of Neural Action Potentials Using a Learned Union of Supports.
Proceedings of the International Conference on Body Sensor Networks, 2011

A low-power digital front-end direct-sampling receiver for flexible radios.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Ultralow-Power Design in Near-Threshold Region.
Proc. IEEE, 2010

Visibility-based beam tracing for soundfield rendering.
Proceedings of the 2010 IEEE International Workshop on Multimedia Signal Processing, 2010

Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Cognitive Radio Wideband Spectrum Sensing Using Multitap Windowing and Power Detection with Threshold Adaptation.
Proceedings of IEEE International Conference on Communications, 2010

Analysis and demonstration of MEM-relay power gating.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
A Flexible DSP Architecture for MIMO Sphere Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Delay Estimation and Sizing of CMOS Logic Using Logical Effort With Slope Correction.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

A 2.89mW 50GOPS 16×16 16-core MIMO sphere decoder in 90nm CMOS.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
A Design Model for Random Process Variability.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Linear analysis of random process variability.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Integrated circuit design with NEM relays.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Flexible VLSI Architecture for Extracting Diversity and Spatial Multiplexing Gains in MIMO Channels.
Proceedings of IEEE International Conference on Communications, 2008

A Multi-Core Sphere Decoder VLSI Architecture for MIMO Communications.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

2007
Power and Area Minimization for Multidimensional Signal Processing.
IEEE J. Solid State Circuits, 2007

ASIC Design and Verification in an FPGA Environment.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Power and Area Efficient VLSI Architectures for Communication Signal Processing.
Proceedings of IEEE International Conference on Communications, 2006

2005
Standby supply voltage minimization for deep sub-micron SRAM.
Microelectron. J., 2005

2004
Methods for true energy-performance optimization.
IEEE J. Solid State Circuits, 2004

SRAM Leakage Suppression by Minimizing Standby Supply Voltage.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2002
A design environment for high-throughput low-power dedicated signal processing systems.
IEEE J. Solid State Circuits, 2002

Methods for true power minimization.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Analysis and design of low-energy flip-flops.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

A design environment for high throughput, low power dedicated signal processing systems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

1997
Semi-automatic Generation of Parallelizable Patterns from Source Code Examples.
Proceedings of the 5th International Workshop on Program Comprehension (WPC '97), May 28-30, 1997, 1997


  Loading...