Deepthi Amuru

Orcid: 0000-0003-0793-3244

According to our database1, Deepthi Amuru authored at least 8 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Links

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Bibliography

2024
Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation.
ACM Trans. Design Autom. Electr. Syst., 2024

MetaCirc: A Meta-learning Approach for Statistical Leakage Estimation Improvement in Digital Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023
AI/ML algorithms and applications in VLSI design and technology.
Integr., November, 2023

Design of Approximate Full Adders for Error Resilient Applications.
Proceedings of the International Conference on Computer and Applications, 2023

2022
Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

2020
An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019


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