Deepesh Gujjar

According to our database, Deepesh Gujjar authored at least 3 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2024

A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range.

Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023

An Innovative Write Circuitry for Enhancing a 3nm L1 Cache Performance Across Wide DVFS Range.

Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2021

A 5nm Wide Voltage Range Ultra High Density SRAM Design for L2/L3 Cache Applications.

Sriharsha Enjapuri, Deepesh Gujjar, Sandipan Sinha, Ramesh Halli, Manish Trivedi

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021