Deepak Nayak

According to our database, Deepak Nayak authored at least 5 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

Reliability Qualification Challenges of SOCs in Advanced CMOS Process Nodes (Invited).

Shou-En Liu, Jian Li, Deepak Nayak, Amit Marathe, Kaushik Balamukundhan, Vishal Gosavi, Ajaykumar Prajapati, Baha Kilic, Mengzhi Pang, Arpit Mittal

Proceedings of the IEEE International Reliability Physics Symposium, 2022

2016

On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs.

Jiajun Shi, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Csaba Andras Moritz

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

How to Cope with Slow Transistors in the Top-tier of Monolithic 3D ICs: Design Studies and CAD Solutions.

Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Tier partitioning strategy to mitigate BEOL degradation and cost issues in monolithic 3D ICs.

Sandeep Kumar Samal, Deepak Nayak, Motoi Ichihashi, Srinivasa Banna, Sung Kyu Lim

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015

Distributed uplink CoMP for small-cell networks.

Shirish Nagaraj, M. R. Raghavendra, Chris Schmidt, Phil Rasky, Deepak Nayak, Xiaoyong Yu, Deepak Pengoria, Michael L. Honig

Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015