Declan Dalton

According to our database, Declan Dalton authored at least 6 papers between 1999 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

A 9-to-12GHz Coupled-RTWO FMCW ADPLL with 97fs RMS Jitter, -120dBc/Hz PN at 1MHz Offset, and With Retrace Time of 12.5ns and 2μs Chirp Settling Time.

Hyman Shanan, Declan Dalton, Vamshi Chillara, Pablo Dato

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2014

A 6.5Mb/s to 11.3Gb/s continuous-rate clock and data recovery.

Jack Kenney, Terry Chen, Larry DeVito, Declan Dalton, Stuart McCracken, Richard Soenneker, Ward S. Titus, Todd S. Weigandt

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2006

A 9.95-11.3-Gb/s XFP Transceiver in 0.13-$\mu{\hbox {m}}$ CMOS.

John G. Kenney, Declan Dalton, Eric Evans, Murat Hayri Eskiyerli, Barry Hilton, Dave Hitchcox, Terence Kwok, Daniel Mulcahy, Chris McQuilkin, Viswabharath Reddy, Siva Selvanayagam, Paul Shepherd, Ward S. Titus, Lawrence DeVito

IEEE J. Solid State Circuits, 2006

A 9.95 to 11.1Gb/s XFP transceiver in 0.13µm CMOS.

Jack Kenney, Declan Dalton, Murat Hayri Eskiyerli, Eric Evans, Barry Hilton, Dave Hitchcox, Terence Kwok, Daniel Mulcahy, Chris McQuilkin, Viswabharath Reddy, Siva Selvanayagam, Paul Shepherd, Ward S. Titus, Larry DeVito

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 12.5-mb/s to 2.7-Gb/s continuous-rate CDR with automatic frequency acquisition and data-rate readback.

Declan Dalton, Kwet Chai, Eric Evans, Mark A. Ferriss, Dave Hitchcox, Paul Murray, Sivanendra Selvanayagam, Paul Shepherd, Lawrence DeVito

IEEE J. Solid State Circuits, 2005

1999

A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications.

Iuri Mehr, Declan Dalton

IEEE J. Solid State Circuits, 1999