Debjit Sinha
According to our database1,
Debjit Sinha
authored at least 31 papers
between 2004 and 2021.
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Bibliography
2021
Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020
2016
Sharing and Re-use of Statistical Timing Macro-Models across Multiple Voltage Domains.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Generation and use of statistical timing macro-models considering slew and load variability.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
2013
Proceedings of the International Symposium on Physical Design, 2013
Speeding up computation of the max/min of a set of gaussians for statistical timing analysis and optimization.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Driver waveform computation for timing analysis with multiple voltage threshold driver models.
Proceedings of the 45th Design Automation Conference, 2008
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Smart bit-width allocation for low power optimization in a systemc based ASIC design environment.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
A unified framework for statistical timing analysis with coupling and multiple input switching.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the 2004 International Symposium on Physical Design, 2004
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004