Debiprasanna Sahoo

According to our database, Debiprasanna Sahoo authored at least 13 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD.

Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2020

Slumber: static-power management for GPGPU register files.

Devashree Tripathy, Hadi Zamani, Debiprasanna Sahoo, Laxmi N. Bhuyan, Manoranjan Satpathy

Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020

Fuzzy fairness controller for NVMe SSDs.

Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam

Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

2019

Formal Modeling and Verification of a Victim DRAM Cache.

Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop

ACM Trans. Design Autom. Electr. Syst., 2019

Multidimensional Grid Aware Address Prediction for GPGPU.

Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Formal Modeling and Verification of NAND Flash Memory Supporting Advanced Operations.

Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Srinivas Pinisetty

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Post-Model Validation of Victim DRAM Caches.

Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018

Formal Modeling and Verification of Controllers for a Family of DRAM Caches.

Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha S. Roop

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ReDRAM: A Reconfigurable DRAM Cache for GPGPUs.

Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam

IEEE Comput. Archit. Lett., 2018

DRAM cache access optimization leveraging line locking in tag cache: work-in-progress.

Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy

Proceedings of the International Conference on Compilers, 2018

CAMO: A novel cache management organization for GPGPUs.

Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi Narayan Bhuyan

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors.

Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016

MSimDRAM: Formal Model Driven Development of a DRAM Simulator.

Debiprasanna Sahoo, Manoranjan Satpathy

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016