Debiprasad Priyabrata Acharya

Orcid: 0000-0003-2211-1783

According to our database1, Debiprasad Priyabrata Acharya authored at least 18 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Online presence:

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Bibliography

2024
Design of robust analog integrated circuit based on process corner performance variability minimization.
Integr., January, 2024

2023
An Intelligent Sensing Framework for Post-Manufacturing Performance Measurement and Healing of CSVCO.
IEEE Trans. Instrum. Meas., 2023

2021
Fast OMP algorithm and its FPGA implementation for compressed sensing-based sparse signal acquisition systems.
IET Circuits Devices Syst., 2021

The impact of GATE thickness variation on FinFET performance parameters.
Proceedings of the 19th OITS International Conference on Information Technology, 2021

2020
Incremental Gaussian Elimination Approach to Implement OMP for Sparse Signal Measurement.
IEEE Trans. Instrum. Meas., 2020

A novel indirect read technique based SRAM with ability to charge recycle and differential read for low power consumption, high stability and performance.
Microelectron. J., 2020

A Low Power Analog-to-Information Converter for Wireless Receivers.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019
Low-Complexity Architecture of Orthogonal Matching Pursuit Based on QR Decomposition.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
A high stable 8T-SRAM with bit interleaving capability for minimization of soft error rate.
Microelectron. J., 2018

2017
Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios.
Microelectron. J., 2017

Current Starving the SRAM Cell: A Strategy to Improve Cell Stability and Power.
Circuits Syst. Signal Process., 2017

2016
QR-based robust diffusion strategies for wireless sensor networks using minimum-Wilcoxon-norm.
IET Signal Process., 2016

Diffusion minimum-Wilcoxon-norm over distributed adaptive networks: Formulation and performance analysis.
Digit. Signal Process., 2016

2014
Low Noise and Fast Locking Phase Locked Loop Using a Variable Delay Element in the Phase Frequency Detector.
J. Low Power Electron., 2014

A New Transmission Gate Cascode Current Mirror Charge Pump for Fast Locking Low Noise PLL.
Circuits Syst. Signal Process., 2014

2012
Design of LC VCO for optimal figure of merit performance using CMODE.
Proceedings of the 1st International Conference on Recent Advances in Information Technology, 2012

2010
Effects of finite register length on fast ICA, bacterial foraging optimization based ICA and constrained genetic algorithm based ICA algorithm.
Digit. Signal Process., 2010

2007
Constrained genetic algorithm based independent component analysis.
Proceedings of the IEEE Congress on Evolutionary Computation, 2007


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