Debendra Das Sharma
Orcid: 0000-0003-1530-7788
According to our database1,
Debendra Das Sharma
authored at least 23 papers
between 1992 and 2024.
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Bibliography
2024
ACM Comput. Surv., November, 2024
Universal Chiplet Interconnect Express: An Open Industry Standard for Memory and Storage Applications.
Computer, January, 2024
Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0.
IEEE Micro, 2024
2023
Compute Express Link (CXL): Enabling Heterogeneous Data-Centric Computing With Heterogeneous Memory Hierarchy.
IEEE Micro, 2023
System on a Package Innovations With Universal Chiplet Interconnect Express (UCIe) Interconnect.
IEEE Micro, 2023
IEEE Micro, 2023
Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express<sup>®</sup> 6.0.
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2023
Invited: Compute Express Link™ (CXL™): An Open Interconnect for Cloud Infrastructure.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
2022
A Low-Latency and Low-Power Approach for Coherency and Memory Protocols on PCI Express 6.0 PHY at 64.0 GT/s With PAM-4 Signaling.
IEEE Micro, 2022
Compute Express Link®: An open industry-standard interconnect enabling heterogeneous data-centric computing.
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2022
2021
PCI Express 6.0 Specification: A Low-Latency, High-Bandwidth, High-Reliability, and Cost-Effective Interconnect With 64.0 GT/s PAM-4 Signaling.
IEEE Micro, 2021
A low latency approach to delivering alternate protocols with coherency and memory semantics using PCI Express® 6.0 PHY at 64.0 GT/s.
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2021
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2021
2020
PCI Express® 6.0 Specification at 64.0 GT/s with PAM-4 signaling: a low latency, high bandwidth, high reliability and cost-effective interconnect.
Proceedings of the IEEE Symposium on High-Performance Interconnects, 2020
2009
Intel® 5520 chipset: An I / O hub chipset for server, workstation, and high end desktop.
Proceedings of the 2009 IEEE Hot Chips 21 Symposium (HCS), 2009
1998
1996
Submesh Allocation in Mesh Multicomputers Using Busy-List: A BestFit Approach with Complete Recognition Capability.
J. Parallel Distributed Comput., 1996
1995
Processor Allocation in Hypercube Multicomputers: Fast and Efficient Strategies for Cubic and Noncubic Allocation.
IEEE Trans. Parallel Distributed Syst., 1995
1994
Proceedings of the 1994 International Conference on Parallel Processing, 1994
1993
A Fast and Efficient Strategy for Submesh Allocation in Mesh-Connected Parallel Computers.
Proceedings of the Fifth IEEE Symposium on Parallel and Distributed Processing, 1993
Fast and Efficient Strategies for Cubic and Non-Cubic Allocation in Hypercube Multiprocessors.
Proceedings of the 1993 International Conference on Parallel Processing, 1993
Proceedings of the Hardware and Software Architectures for Fault Tolerance, 1993
1992
Proceedings of the Fourth IEEE Symposium on Parallel and Distributed Processing, 1992