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Debdut Biswas

Orcid: 0000-0002-1825-5082

According to our database1, Debdut Biswas authored at least 4 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

2019
2020
2021
2022
2023
2024
0
1
2
3
1
1
1
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Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A reference sampling ΔΣ subsampling PLL.
[BibTeX]
[DOI]
Debdut Biswas
Integr., 2024

2022
Spur Reduction Circuit for Fractional-N PLLs.
[BibTeX]
[DOI]
Debdut Biswas
Circuits Syst. Signal Process., 2022

2019
Spur reduction architecture for multiphase fractional PLLs.
[BibTeX]
[DOI]
Debdut Biswas
,
Tarun Kanti Bhattacharyya
IET Circuits Devices Syst., 2019

A Model of Spurs for Delta-Sigma Fractional PLLs.
[BibTeX]
[DOI]
Debdut Biswas
,
Tarun Kanti Bhattacharyya
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019


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