Debdeep Mukhopadhyay

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Rapid detection of rowhammer attacks using dynamic skewed hash tree.

[BibT_eX]

[DOI]

Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

PUFSSL: An OpenSSL Extension for PUF based Authentication.

[BibT_eX]

[DOI]

Sweta Pati

Debashis Mahata

Mukesh M. Prabhu

Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECC Application in GF(p).

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Breaking Redundancy-Based Countermeasures with Random Faults and Power Side Channel.

[BibT_eX]

[DOI]

Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

Efficient Secure k-Nearest Neighbours over Encrypted Data.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Extending Database Technology, 2018

DFARPA: Differential fault attack resistant physical design automation.

[BibT_eX]

[DOI]

Anupam Chattopadhyay

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Trustworthy proofs for sensor data using FPGA based physically unclonable functions.

[BibT_eX]

[DOI]

Urbi Chatterjee

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Side-Channel Assisted Malware Classifier with Gradient Descent Correction for Embedded Platforms.

[BibT_eX]

[DOI]

Thambipillai Srikanthan

Proceedings of the PROOFS 2018, 2018

POSTER: Authenticated Key-Exchange Protocol for Heterogeneous CPS.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Asia Conference on Computer and Communications Security, 2018

Hardware Acceleration of Searchable Encryption.

[BibT_eX]

[DOI]

Proceedings of the 2018 ACM SIGSAC Conference on Computer and Communications Security, 2018

2017

Security Analysis of Arbiter PUF and Its Lightweight Compositions Under Predictability Test.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2017

Fault Space Transformation: A Generic Approach to Counter Differential Fault Analysis and Differential Fault Intensity Analysis on AES-Like Block Ciphers.

[BibT_eX]

[DOI]

Partha Pratim Chakrabarti

IEEE Trans. Inf. Forensics Secur., 2017

A PUF-Based Secure Communication Protocol for IoT.

[BibT_eX]

[DOI]

Urbi Chatterjee

ACM Trans. Embed. Comput. Syst., 2017

An Improved DCM-Based Tunable True Random Number Generator for Xilinx FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2017

A Combined Power and Fault Analysis Attack on Protected Grain Family of Stream Ciphers.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Provably Secure Key-Aggregate Cryptosystems with Broadcast Aggregate Keys for Online Data Sharing on the Cloud.

[BibT_eX]

[DOI]

Yash Shrivastava

IEEE Trans. Computers, 2017

Construction of Rotation Symmetric S-Boxes with High Nonlinearity and Improved DPA Resistivity.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Remote dynamic partial reconfiguration: A threat to Internet-of-Things and embedded security applications.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

An Evaluation of Lightweight Block Ciphers for Resource-Constrained Applications: Area, Performance, and Security.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2017

Two Efficient Fault-Based Attacks on CLOC and SILC.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2017

Fault Tolerant Infective Countermeasure for AES.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2017

Editorial for the Special Issue in Journal of Hardware and Systems Security (HaSS) Based on Selected Papers from 6th International Conference on Security, Privacy and Applied Cryptographic Engineering (SPACE 2016).

[BibT_eX]

[DOI]

Vishal Saraswat

J. Hardw. Syst. Secur., 2017

Formal fault analysis of branch predictors: attacking countermeasures of asymmetric key ciphers.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2017

Lightweight Design Choices for LED-like Block Ciphers.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Differential Fault Analysis Automation.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Lightweight Symmetric-Key Hidden Vector Encryption without Pairings.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Spot the Black Hat in a Dark Room: Parallelized Controlled Access Searchable Encryption on FPGAs.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Encrypt-Augment-Recover: Computationally Function Private Predicate Encryption in the Public-Key Setting.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

One Plus One is More than Two: A Practical Combination of Power and Fault Analysis Attacks on PRESENT and PRESENT-like Block Ciphers.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

A Practical Fault Attack on ARX-like Ciphers with a Case Study on ChaCha20.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

PUF+IBE: Blending Physically Unclonable Functions with Identity Based Encryption for Authentication and Key Exchange in IoTs.

[BibT_eX]

[DOI]

Debashis Mahata

Mukesh M. Prabhu

IACR Cryptol. ePrint Arch., 2017

Leakage-Resilient Tweakable Encryption from One-Way Functions.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Template Attack on Blinded Scalar Multiplication with Asynchronous perf-ioctl Calls.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Performance Counters to Rescue: A Machine Learning based safeguard against Micro-architectural Side-Channel-Attacks.

[BibT_eX]

[DOI]

Manaar Alam

Sourangshu Bhattacharya

IACR Cryptol. ePrint Arch., 2017

Redefining the transparency order.

[BibT_eX]

[DOI]

Des. Codes Cryptogr., 2017

Tackling the Time-Defence: An Instruction Count Based Micro-architectural Side-Channel Attack on Block Ciphers.

[BibT_eX]

[DOI]

Manaar Alam

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2017

Opening pandora's box: Implication of RLUT on secure FPGA applications and IP security.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Side Channel Evaluation of PUF-Based Pseudorandom Permutation.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Conference on Digital System Design, 2017

An Automated Framework for Exploitable Fault Identification in Block Ciphers - A Data Mining Approach.

[BibT_eX]

[DOI]

Proceedings of the PROOFS 2017, 2017

Using Tweaks To Design Fault Resistant Ciphers (Full Version).

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, 2017

2016

Theory and Application of Delay Constraints in Arbiter PUF.

[BibT_eX]

[DOI]

Urbi Chatterjee

Hitesh Kapoor

ACM Trans. Embed. Comput. Syst., 2016

Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures.

[BibT_eX]

[DOI]

Sanjay Burman

Seetal Potluri

Kamakoti Veezhinathan

J. Low Power Electron., 2016

Template attack on SPA and FA resistant implementation of Montgomery ladder.

[BibT_eX]

[DOI]

IET Inf. Secur., 2016

Side-Channel Watchdog: Run-Time Evaluation of Side-Channel Vulnerability in FPGA-Based Crypto-systems.

[BibT_eX]

[DOI]

Souvik Sonar

IACR Cryptol. ePrint Arch., 2016

Fault Tolerant Implementations of Delay-based Physically Unclonable Functions on FPGA.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Architectural Bias: a Novel Statistical Metric to Evaluate Arbiter PUF Variants.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

What Lies Ahead: Extending TVLA Testing Methodology Towards Success Rate.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

A Practical Template Attack on MICKEY-128 2.0 Using PSO Generated IVs and LS-SVM.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Curious case of Rowhammer: Flipping Secret Exponent Bits using Timing Analysis.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Exploiting Safe Error based Leakage of RFID Authentication Protocol using Hardware Trojan Horse.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

PUFs as Promising Tools for Security in Internet of Things.

[BibT_eX]

[DOI]

IEEE Des. Test, 2016

Embedded Security.

[BibT_eX]

[DOI]

Ingrid Verbauwhede

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Fault Based Almost Universal Forgeries on CLOC and SILC.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Fault Injection Attacks: Attack Methodologies, Injection Techniques and Protection Mechanisms - A Tutorial.

[BibT_eX]

[DOI]

Shivam Bhasin

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Secure public key hardware for IoT applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

SmashClean: A hardware level mitigation to stack smashing attacks in OpenRISC.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Accelerating OpenSSL's ECC with low cost reconfigurable hardware.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Integrated Circuits, 2016

A Formal Security Analysis of Even-Odd Sequential Prefetching in Profiled Cache-Timing Attacks.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016

Shuffling across rounds: A lightweight strategy to counter side-channel attacks.

[BibT_eX]

[DOI]

Praveen Kumar Vadnala

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Parsimonious design strategy for linear layers with high diffusion in block ciphers.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Inner collisions in ECC: Vulnerabilities of complete addition formulas for NIST curves.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Testability Based Metric for Hardware Trojan Vulnerability Assessment.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Remote Dynamic Clock Reconfiguration Based Attacks on Internet of Things Applications.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Improved Atomicity to Prevent HCCA on NIST Curves.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM International Workshop on ASIA Public-Key Cryptography, 2016

2015

A PUF-Enabled Secure Architecture for FPGA-Based IoT Applications.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2015

A Case of Lightweight PUF Constructions: Cryptanalysis and Machine Learning Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Reaching the Limit of Nonprofiling DPA.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Micro-Architectural Analysis of Time-Driven Cache Attacks: Quest for the Ideal Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Security analysis of concurrent error detection against differential fault analysis.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2015

Improved Test Pattern Generation for Hardware Trojan Detection using Genetic Algorithm and Boolean Satisfiability.

[BibT_eX]

[DOI]

Srinivasa Shashank Nuthakki

Anshul

IACR Cryptol. ePrint Arch., 2015

Reconfigurable LUT: Boon or Bane for Secure Applications.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

ECC on Your Fingertips: A Single Instruction Approach for Lightweight ECC Design in GF (p).

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Dynamic Key-Aggregate Cryptosystem on Elliptic Curves for Online Data Sharing.

[BibT_eX]

[DOI]

Yash Shrivastava

IACR Cryptol. ePrint Arch., 2015

Using Tweaks To Design Fault Resistant Ciphers.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Using State Space Encoding To Counter Biased Fault Attacks on AES Countermeasures.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Exploiting the Order of Multiplier Operands: A Low Cost Approach for HCCA Resistance.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Combined Side-Channel and Fault Analysis Attack on Protected Grain Family of Stream Ciphers.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Who watches the watchmen? : Utilizing Performance Monitors for Compromising keys of RSA on Intel Platforms.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Construction of RSBFs with improved cryptographic properties to resist differential fault attack on grain family of stream ciphers.

[BibT_eX]

[DOI]

Cryptogr. Commun., 2015

Tutorial T7: Physically Unclonable Function: A Promising Security Primitive for Internet of Things.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Reconfigurable LUT: A Double Edged Sword for Security-Critical Applications.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2015

Modified Transparency Order Property: Solution or Just Another Attempt.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2015

From theory to practice of private circuit: A cautionary note.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A practical DPA on Grain v1 using LS-SVM.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

A Novel Attack on a FPGA based True Random Number Generator.

[BibT_eX]

[DOI]

Proceedings of the 10th Workshop on Embedded Systems Security, 2015

Towards Ideal Arbiter PUF Design on Xilinx FPGA: A Practitioner's Perspective.

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Efficient attacks on robust ring oscillator PUF with enhanced challenge-response set.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Improved practical differential fault analysis of grain-128.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A Biased Fault Attack on the Time Redundancy Countermeasure for AES.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2015

2014

Differential Fault Analysis on the families of SIMON and SPECK ciphers.

[BibT_eX]

[DOI]

Harshal Tupsamudre

Shikha Bisht

IACR Cryptol. ePrint Arch., 2014

Lightweight Diffusion Layer from the kth root of the MDS Matrix.

[BibT_eX]

[DOI]

Souvik Kolay

IACR Cryptol. ePrint Arch., 2014

NREPO: Normal Basis Recomputing with Permuted Operands.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2014

Multi-Bit Differential Fault Analysis of Grain-128 with Very Weak Assumptions.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2014

Redefining the Transparency Order.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2014

Fault Attack revealing Secret Keys of Exponentiation Algorithms from Branch Prediction Misses.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2014

Cryptanalysis of Composite PUFs (Extended abstract-invited talk).

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014

Khudra: A New Lightweight Block Cipher for FPGAs.

[BibT_eX]

[DOI]

Souvik Kolay

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2014

Fibonacci LFSR vs. Galois LFSR: Which is More Vulnerable to Power Attacks?

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2014

Composite PUF: A new design paradigm for Physically Unclonable Functions on FPGA.

[BibT_eX]

[DOI]

Hitesh Kapoor

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Circuits and Synthesis Mechanism for Hardware Design to Counter Power Analysis Attacks.

[BibT_eX]

[DOI]

Partha De

Kunal Banerjee

Chittaranjan A. Mandal

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST Curves.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

On the Optimal Pre-processing for Non-profiling Differential Power Analysis.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2014

Destroying Fault Invariant with Randomization - A Countermeasure for AES Against Differential Fault Attacks.

[BibT_eX]

[DOI]

Harshal Tupsamudre

Shikha Bisht

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2014, 2014

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet.

[BibT_eX]

[DOI]

Sezer Gören

Proceedings of the 9th Workshop on Embedded Systems Security, 2014

DRECON: DPA Resistant Encryption by Construction.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology - AFRICACRYPT 2014, 2014

Highly Compact Automated Implementation of Linear CA on FPGAs.

[BibT_eX]

[DOI]

Ayan Palchaudhuri

Mohammad Salman

Sreemukh Kardas

Proceedings of the Cellular Automata, 2014

Hardware Security - Design, Threats, and Safeguards.

[BibT_eX]

[DOI]

CRC Press, ISBN: 978-1-439-89583-2, 2014

2013

Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Formalizing the Effect of Feistel Cipher Structures on Differential Cache Attacks.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2013

Constrained Search for a Class of Good Bijective S-Boxes With Improved DPA Resistivity.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2013

Differential fault analysis of AES: towards reaching its limits.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2013

Rain: Reversible Addition with Increased Nonlinearity.

[BibT_eX]

[DOI]

Jaydeb Bhaumik

Int. J. Netw. Secur., 2013

SNR to Success Rate: Reaching the Limit of Non-Profiling DPA.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2013

Pushing the Limit of Non-Profiling DPA using Multivariate Leakage Model.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2013

A Fault Analysis Perspective for Testing of Secured SoC Cores.

[BibT_eX]

[DOI]

Sk Subidh Ali

IEEE Des. Test, 2013

Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2013

Design of low area-overhead ring oscillator PUF with large challenge space.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Unraveling timewarp: what all the fuzz is about?

[BibT_eX]

[DOI]

Proceedings of the HASP 2013, 2013

On-line testing for differential fault attacks in cryptographic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Design and implementation of rotation symmetric S-boxes with high nonlinearity and high DPA resilience.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Improved Differential Fault Analysis of CLEFIA.

[BibT_eX]

[DOI]

Proceedings of the 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2013

Lightweight cipher implementations on embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2013

PERMS: A Bit Permutation Instruction for Accelerating Software Cryptography.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Designing DPA Resistant Circuits Using BDD Architecture and Bottom Pre-charge Logic.

[BibT_eX]

[DOI]

Partha De

Kunal Banerjee

Chittaranjan A. Mandal

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Role of power grid in side channel attack and power-grid-aware secure design.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Multivariate Leakage Model for Improving Non-profiling DPA on Noisy Power Traces.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - 9th International Conference, 2013

2012

Boosting Profiled Cache Timing Attacks With A Priori Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2012

CAvium - Strengthening Trivium Stream Cipher Using Cellular Automata.

[BibT_eX]

[DOI]

Sandip Karmakar

J. Cell. Autom., 2012

Generalized high speed Itoh-Tsujii multiplicative inversion architecture for FPGAs.

[BibT_eX]

[DOI]

Integr., 2012

Constrained Search for a Class of Good S-Boxes with Improved DPA Resistivity.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2012

Provably Secure Concurrent Error Detection Against Differential Fault Analysis.

[BibT_eX]

[DOI]

Xiaofei Guo

Ramesh Karri

IACR Cryptol. ePrint Arch., 2012

Protecting Last Four Rounds of CLEFIA is Not Enough Against Differential Fault Analysis.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2012

Design for Security of Block Cipher S-Boxes to Resist Differential Power Attacks.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on VLSI Design, 2012

An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Effect of Malicious Hardware Logic on Circuit Reliability.

[BibT_eX]

[DOI]

Sanjay Burman

Ayan Palchaudhuri

Pranav Singh

Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012

Hardware Prefetchers Leak: A Revisit of SVF for Cache-Timing Attacks.

[BibT_eX]

[DOI]

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

A Parallel Architecture for Koblitz Curve Scalar Multiplications on FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Improved Differential Cache Attacks on SMS4.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - 8th International Conference, 2012

Differential Fault Analysis of Twofish.

[BibT_eX]

[DOI]

Proceedings of the Information Security and Cryptology - 8th International Conference, 2012

Pushing the Limits of High-Speed GF(2 m ) Elliptic Curve Scalar Multiplication on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

Generating Expander Graphs Using Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2012

2011

Revisiting the Itoh-Tsujii Inversion Algorithm for FPGA Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2011

Petrel: Power and Timing Attack Resistant Elliptic Curve Scalar Multiplier Based on Programmable GF(p) Arithmetic Unit.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A Parallel Efficient Architecture for Large Cryptographically Robust n × k (k>n/2) Mappings.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2011

Fault Attack, Countermeasures on Pairing Based Cryptography.

[BibT_eX]

[DOI]

Int. J. Netw. Secur., 2011

Scalar Multiplication on Koblitz Curves using tau2-NAF.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2011

TweLEX: A Tweaked Version of the LEX Stream Cipher.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2011

Security of Prime Field Pairing Cryptoprocessor Against Differential Power Attack.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2011

Differential Fault Analysis of the Advanced Encryption Standard Using a Single Fault.

[BibT_eX]

[DOI]

Proceedings of the Information Security Theory and Practice. Security and Privacy of Mobile Devices in Wireless Communication, 2011

PKDPA: An Enhanced Probabilistic Differential Power Attack Methodology.

[BibT_eX]

[DOI]

Dhiman Saha

Proceedings of the Progress in Cryptology - INDOCRYPT 2011, 2011

An Enhanced Differential Cache Attack on CLEFIA for Large Cache Lines.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology - INDOCRYPT 2011, 2011

Accelerating Itoh-Tsujii multiplicative inversion algorithm for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A Differential Fault Analysis on AES Key Schedule Using Single Fault.

[BibT_eX]

[DOI]

Proceedings of the 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2011

Theoretical modeling of the Itoh-Tsujii Inversion algorithm for enhanced performance on k-LUT based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Multi-level attacks: An emerging security concern for cryptographic hardware.

[BibT_eX]

[DOI]

Swarup Bhunia

Proceedings of the Design, Automation and Test in Europe, 2011

Cryptanalysis of CLEFIA Using Differential Methods with Cache Trace Patterns.

[BibT_eX]

[DOI]

Proceedings of the Topics in Cryptology - CT-RSA 2011, 2011

Differential Fault Analysis of AES-128 Key Schedule Using a Single Multi-byte Fault.

[BibT_eX]

[DOI]

Proceedings of the Smart Card Research and Advanced Applications, 2011

Testability of Cryptographic Hardware and Detection of Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

An Improved Differential Fault Analysis on AES-256.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology - AFRICACRYPT 2011, 2011

2010

Group Properties of Non-linear Cellular Automata.

[BibT_eX]

[DOI]

J. Cell. Autom., 2010

Differential Cache Trace Attack Against CLEFIA.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2010

Differential Fault Analysis of AES using a Single Multiple-Byte Fault.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2010

Acceleration of Differential Fault Analysis of the Advanced Encryption Standard Using Single Fault.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2010

Pinpointing Cache Timing Attacks on AES.

[BibT_eX]

[DOI]

Mainack Mondal

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

New Pseudo Near Collision Attack on Tiger.

[BibT_eX]

Dibyendu Mallik

Proceedings of the SECRYPT 2010, 2010

High Speed Flexible Pairing Cryptoprocessor on FPGA Platform.

[BibT_eX]

[DOI]

Proceedings of the Pairing-Based Cryptography - Pairing 2010, 2010

High speed Fp multipliers and adders on FPGA platform.

[BibT_eX]

[DOI]

Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

d-Monomial Tests of Nonlinear Cellular Automata for Cryptographic Design.

[BibT_eX]

[DOI]

Sandip Karmakar

Proceedings of the Cellular Automata, 2010

2009

Effect of glitches against masked AES S-box implementation and countermeasure.

[BibT_eX]

[DOI]

IET Inf. Secur., 2009

Differential Fault Analysis of the Advanced Encryption Standard using a Single Fault.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2009

A Diagonal Fault Attack on the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Dhiman Saha

IACR Cryptol. ePrint Arch., 2009

Cache Timing Attacks on Clefia.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology, 2009

A new fault attack on the advanced encryption standard hardware.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

An Improved Fault Based Attack of the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology, 2009

2008

VLSI Architecture of a Cellular Automata based One-Way Function.

[BibT_eX]

[DOI]

Pallavi Joshi

J. Comput., 2008

Customizing Cellular Message Encryption Algorithm.

[BibT_eX]

[DOI]

Int. J. Netw. Secur., 2008

Power Attack Resistant Efficient FPGA Architecture for Karatsuba Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

High Speed Compact Elliptic Curve Cryptoprocessor for FPGA Platforms.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology, 2008

Scan Based Side Channel Attacks on Stream Ciphers and Their Counter-Measures.

[BibT_eX]

[DOI]

Proceedings of the Progress in Cryptology, 2008

Theory of Composing Non-linear Machines with Predictable Cyclic Structures.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2008

2007

Secured Flipped Scan-Chain Model for Crypto-Architecture.

[BibT_eX]

[DOI]

Gaurav Sengar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Hierarchical Verification of Galois Field Circuits.

[BibT_eX]

[DOI]

Gaurav Sengar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Theory of a Class of Complemented Group Cellular Automata and Its Application to Cryptography.

[BibT_eX]

[DOI]

J. Cell. Autom., 2007

An Efficient Design of Cellular Automata Based Cryptographically Robust One-Way Function.

[BibT_eX]

[DOI]

Pallavi Joshi

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Design of a Differential Power Analysis Resistant Masked AES S-Box.

[BibT_eX]

[DOI]

Kundan Kumar

Proceedings of the Progress in Cryptology, 2007

LFSR Based Stream Ciphers Are Vulnerable to Power Attacks.

[BibT_eX]

[DOI]

Sanjay Burman

Kamakoti Veezhinathan

Proceedings of the Progress in Cryptology, 2007

An area optimized reconfigurable encryptor for AES-Rijndael.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Strengthening NLS Against Crossword Puzzle Attack.

[BibT_eX]

[DOI]

Debojyoti Bhattacharya

Dhiman Saha

Proceedings of the Information Security and Privacy, 12th Australasian Conference, 2007

2006

An integrated DFT solution for mixed-signal SOCs.

[BibT_eX]

[DOI]

Shibaji Banerjee

C. V. G. Rao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Programmable Parallel Structure to perform Galois Field Exponentiation.

[BibT_eX]

[DOI]

Kundan Kumar

Proceedings of the 9th International Conference in Information Technology, 2006

Generation of Expander Graphs Using Cellular Automata and Its Applications to Cryptography.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2006

A Cellular Automata Based Approach for Generation of Large Primitive Polynomial and Its Application to RS-Coded MPSK Modulation.

[BibT_eX]

[DOI]

Debojyoti Bhattacharya

Proceedings of the Cellular Automata, 2006

2005

Key Mixing in Block Ciphers through Addition modulo 2n.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2005

Design and Analysis of a Robust and Efficient Block Cipher using Cellular Automata.

[BibT_eX]

[DOI]

Pallavi Joshi

IACR Cryptol. ePrint Arch., 2005

An Efficient End to End Design of Rijndael Cryptosystem in 0.18 ? CMOS.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Computer Aided Test (CAT) Tool for Mixed Signal SOCs.

[BibT_eX]

[DOI]

Shibaji Banerjee

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

CCMEA: Customized Cellular Message Encryption Algorithm for Wireless Networks.

[BibT_eX]

[DOI]

Abhishek Chaudhary

Arvind Nebhnani

Proceedings of the Information Systems Security, First International Conference, 2005

Cellular automata based key agreement.

[BibT_eX]

Proceedings of the ICETE 2005, 2005

CryptoScan: A Secured Scan Chain Architecture.

[BibT_eX]

[DOI]

Shibaji Banerjee

Bhargab B. Bhattacharya

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Cellular Automata : An Ideal Candidate for a Block Cipher.

[BibT_eX]

[DOI]

Proceedings of the Distributed Computing and Internet Technology, 2004

Characterization of a Class of Complemented Group Cellular Automata.

[BibT_eX]

[DOI]

Proceedings of the Cellular Automata, 2004

2002

Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch.

[BibT_eX]

[DOI]

Subhayu Basu