Debasri Saha

Orcid: 0000-0002-7935-0980

According to our database1, Debasri Saha authored at least 50 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Scalable Test Generation to Trigger Rare Targets in High-Level Synthesizable IPs for Cloud FPGAs.
CoRR, 2024

2023
AgEncID: Aggregate Encryption Individual Decryption of Key for FPGA Bitstream IP Cores in Cloud.
CoRR, 2023

2022
Faster search of clustered marked states with lackadaisical quantum walks.
Quantum Inf. Process., 2022

Test Generation for SystemC designs by interlaced Greybox Fuzzing and Concolic Execution.
CoRR, 2022

GreyConE: Greybox Fuzzing + Concolic Execution Guided Test Generation for High Level Designs.
Proceedings of the IEEE International Test Conference, 2022

2021
Minimization of WCRT with Recovery Assurance from Hardware Trojans for Tasks on FPGA-based Cloud.
ACM Trans. Embed. Comput. Syst., 2021

Circuit Design for k-Coloring Problem and Its Implementation in Any Dimensional Quantum System.
SN Comput. Sci., 2021

FuCE: Fuzzing+Concolic Execution guided Trojan Detection in Synthesizable Hardware Designs.
CoRR, 2021

"Fog-Miner" Based Resource Aware scalable Framework Development in IoT platform.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021

2020
Dynamic power-aware scheduling of real-time tasks for FPGA-based cyber physical systems against power draining hardware trojan attacks.
J. Supercomput., 2020

Asymptotically Improved Grover's Algorithm in any Dimensional Quantum System with Novel Decomposed n-qudit Toffoli Gate.
CoRR, 2020

Circuit Design for K-coloring Problem and it's Implementation on Near-term Quantum Devices.
CoRR, 2020

A Multi-Agent Co-operative Model to Facilitate Criticality based Reliability for Mixed Critical Task Execution on FPGA based Cloud Environment.
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020

Ensuring Green Computing in Reconfigurable Hardware based Cloud Platforms from Hardware Trojan Attacks.
Proceedings of the 2020 IEEE Region 10 Conference, 2020

Circuit Design for K-coloring Problem and its Implementation on Near-term Quantum Devices.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

Blockchain Technology Enabled Pay Per Use Licensing Approach for Hardware IPs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Guided GA-Based Multiobjective Optimization of Placement and Assignment of TSVs in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components.
ACM Trans. Embed. Comput. Syst., 2019

Criticality based reliability against hardware Trojan attacks for processing of tasks on reconfigurable hardware.
Microprocess. Microsystems, 2019

A CAD approach for pre-layout optimal PDN design and its post-layout verification.
Microprocess. Microsystems, 2019

Zero Knowledge Authentication for Reuse of IPs in Reconfigurable Platforms.
Proceedings of the TENCON 2019, 2019

2018
SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Reliability Driven Mixed Critical Tasks Processing on FPGAs Against Hardware Trojan Attacks.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

FPGA-Based Novel Speech Enhancement System Using Microphone Activity Detector.
Proceedings of the Advanced Computing and Systems for Security, 2018

2017
Coherence based dual microphone speech enhancement technique using FPGA.
Microprocess. Microsystems, 2017

Real-Time SoC Security against Passive Threats Using Crypsis Behavior of Geckos.
ACM J. Emerg. Technol. Comput. Syst., 2017

Multi-objective Optimization of Placement and Assignment of TSVs in 3D ICs.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

Self Aware SoC Security to Counteract Delay Inducing Hardware Trojans at Runtime.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage.
Proceedings of the 7th International Symposium on Embedded Computing and System Design, 2017

Dual Microphone Sound Source Localization Using Reconfigurable Hardware.
Proceedings of the Computational Intelligence, Communications, and Business Analytics, 2017

2016
Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip.
IET Comput. Digit. Tech., 2016

Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC.
Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

2015
Watermarking in Hard Intellectual Property for Pre-Fab and Post-Fab Verification.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Pre-Layout Decoupling Capacitance Estimation and Allocation for Noise-Aware Crypto-System on Chip Applications.
J. Low Power Electron., 2015

RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Adaptive Multilayer Routing for Incremental Design of an SoC.
Proceedings of the 4th International Conference on Frontiers in Intelligent Computing: Theory and Applications, 2015

2014
Analysis of power distribution network for some cryptocores.
Proceedings of the 2014 International Conference on Advances in Computing, 2014

Analysis of Secret Key Revealing Trojan Using Path Delay Analysis for Some Cryptocores.
Proceedings of the 3rd International Conference on Frontiers of Intelligent Computing: Theory and Applications (FICTA) 2014, 2014

Trusted sharing of intellectual property in electronic hardware design.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

2012
Secure Public Verification of IP Marks in FPGA Design Through a Zero-Knowledge Protocol.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2011
SoC: A Real Platform for IP Reuse, IP Infringement, and IP Protection.
VLSI Design, 2011

Cone-based placement for field programmable gate arrays.
IET Comput. Digit. Tech., 2011

2010
Robust intellectual property protection of VLSI physical design.
IET Comput. Digit. Tech., 2010

A Unified Approach for IP Protection across Design Phases in a Packaged Chip.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2009
Encoding of Floorplans through Deterministic Perturbation.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Secure Leakage-Proof Public Verification of IP Marks in VLSI Physical Design.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008
An Analytical Approach to Direct IP Protection of VLSI Floorplans.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

2007
A Novel Scheme for Encoding and Watermark Embedding in VLSI Physical Design for IP Protection.
Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Fast Robust Intellectual Property Protection for VLSI Physical Design.
Proceedings of the 10th International Conference on Information Technology, 2007

2006
A Mimetic Algorithm for Refinement of Lower Bound of Number of Tracks in Channel Routing Problem.
Proceedings of the Intelligent Information Processing III, 2006


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