Debashis Bhattacharya

According to our database, Debashis Bhattacharya authored at least 22 papers between 1988 and 2005.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2005

Transistor-Level Optimization of Digital Designs with Flex Cells.

Rob Roy, Debashis Bhattacharya, Vamsi Boppana

Computer, 2005

1999

Instruction-Driven Wake-Up Mechanisms for Snoopy TAP Controller.

Debashis Bhattacharya

Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

1998

Hierarchical Test Access Architecture for Embedded Cores in an Integrated Circuit.

Debashis Bhattacharya

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997

Invariance of stereo images via the theory of complex moments.

Debashis Bhattacharya, Satyabroto Sinha

Pattern Recognit., 1997

Algorithms for Low Power FIR Filter Realization Using Differential Coefficients.

Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit.

Debashis Bhattacharya, Smith Freeman, Bill Lin

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Optimizing computations in a transposed direct form realization of floating-point LTI-FIR systems.

Naushik Sankarayya, Kaushik Roy, Debashis Bhattacharya

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1995

An efficient method for generating exhaustive test sets.

Ted Stanion, Debashis Bhattacharya, Carl Sechen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Test Generation for Path Delay Faults Using Binary Decision Diagrams.

Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal

IEEE Trans. Computers, 1995

A three-stage partial scan design method to ease ATPG.

Shang-E Tai, Debashis Bhattacharya

J. Electron. Test., 1995

1994

A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph.

Shang-E Tai, Debashis Bhattacharya

Proceedings of the Seventh International Conference on VLSI Design, 1994

1993

Architecture of a Min-Max Simulator on MARS.

Kumar N. Lalgudi, Debashis Bhattacharya, Prathima Agrawal

Proceedings of the Sixth International Conference on VLSI Design, 1993

Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph.

Shang-E Tai, Debashis Bhattacharya

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Boolean algebraic test generation using a distributed system.

Debashis Bhattacharya, Prathima Agrawal

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions.

Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal

Proceedings of the 29th Design Automation Conference, 1992

1991

TSUNAMI: A Path Oriented Scheme for Algebraic Test Generation.

Ted Stanion, Debashis Bhattacharya

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

1990

Designing for high-level test generation.

Debashis Bhattacharya, John P. Hayes

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

A hierarchical test generation methodology for digital circuits.

Debashis Bhattacharya, John P. Hayes

J. Electron. Test., 1990

CMP3F: a high speed fault simulator for the Connection Machine.

Ajit Agrawal, Debashis Bhattacharya

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

Binary to Quaternary Encoding in Clocked CMOS Circuits Using Weak Buffer.

Debashis Bhattacharya

Proceedings of the 20th International Symposium on Multiple-Valued Logic, 1990

1989

High-Level Test Generation for VLSI.

Debashis Bhattacharya, Brian T. Murray, John P. Hayes

Computer, 1989

1988

Hierarchical modeling and test generation for digital circuits.

Debashis Bhattacharya

PhD thesis, 1988