Debapriya Chatterjee

According to our database, Debapriya Chatterjee authored at least 17 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Verifying Memory Confidentiality and Integrity of Intel TDX Trusted Execution Environments.

Hasini Witharana, Debapriya Chatterjee, Prabhat Mishra

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

2022

Return-oriented programming protection in the IBM POWER10.

José E. Moreira, Debapriya Chatterjee, Kattamuri Ekanadham, Arnold Flores

Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2018

Addressing verification challenges of heterogeneous systems based on IBM POWER9.

Klaus-Dieter Schubert, Syed Saif Abrar, Duane Averill, Ellen Bauman, Aaron C. Brown, Ron Cash, Debapriya Chatterjee, John Gullickson, Mark Nelson, Kevin A. Pasnik, Krishnan Sugavanam

IBM J. Res. Dev., 2018

2014

ArChiVED: Architectural checking via event digests for high performance validation.

Chang-Hong Hsu, Debapriya Chatterjee, Ronny Morad, Raviv Gal, Valeria Bertacco

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

Harnessing Simulation Acceleration to Solve the Digital Design Verification Challenge.

Debapriya Chatterjee

PhD thesis, 2013

Hybrid checking for microarchitectural validation of microprocessor designs on acceleration platforms.

Debapriya Chatterjee, Biruk Mammo, Doowon Lee, Raviv Gal, Ronny Morad, Amir Nahir, Avi Ziv, Valeria Bertacco

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

On the use of GP-GPUs for accelerating compute-intensive EDA applications.

Valeria Bertacco, Debapriya Chatterjee, Nicola Bombieri, Franco Fummi, Sara Vinco, Anirudh M. Kaushik, Hiren D. Patel

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Approximating checkers for simulation acceleration.

Biruk Mammo, Debapriya Chatterjee, Dmitry Pidan, Amir Nahir, Avi Ziv, Ronny Morad, Valeria Bertacco

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

SAGA: SystemC acceleration on GPU architectures.

Sara Vinco, Debapriya Chatterjee, Valeria Bertacco, Franco Fummi

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Checking architectural outputs instruction-by-instruction on acceleration platforms.

Debapriya Chatterjee, Anatoly Koyfman, Ronny Morad, Avi Ziv, Valeria Bertacco

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

SystemC simulation on GP-GPUs: CUDA vs. OpenCL.

Nicola Bombieri, Sara Vinco, Valeria Bertacco, Debapriya Chatterjee

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

2011

Gate-Level Simulation with GPU Computing.

Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco

ACM Trans. Design Autom. Electr. Syst., 2011

Simulation-based signal selection for state restoration in silicon debug.

Debapriya Chatterjee, Calvin McCarter, Valeria Bertacco

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

EQUIPE: Parallel equivalence checking with GP-GPUs.

Debapriya Chatterjee, Valeria Bertacco

Proceedings of the 28th International Conference on Computer Design, 2010

2009

Activity-based refinement for abstraction-guided simulation.

Debapriya Chatterjee, Valeria Bertacco

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

GCS: High-performance gate-level simulation with GPGPUs.

Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco

Proceedings of the Design, Automation and Test in Europe, 2009

Event-driven gate-level simulation with GP-GPUs.

Debapriya Chatterjee, Andrew DeOrio, Valeria Bertacco

Proceedings of the 46th Design Automation Conference, 2009