Debapriya Basu Roy

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Design of a Lightweight Fast Fourier Transformation for FALCON using Hardware-Software Co-Design.

[BibT_eX]

[DOI]

Suraj Mandal

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Automatic Generation of Modular Multipliers Upon Pseudo-Mersenne Primes Using DSP Blocks on FPGAs.

[BibT_eX]

[DOI]

Shree Harish S

Proceedings of the 27th Euromicro Conference on Digital System Design, 2024

Multiplierless Design of High-Speed Very Large Constant Multiplications.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

A Comparative Analysis between Karatsuba, Toom-Cook and NTT Multiplier for Polynomial Multiplication in NTRU on FPGA.

[BibT_eX]

[DOI]

Harish Prasad Allam

Suraj Mandal

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2023

2022

Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography.

[BibT_eX]

[DOI]

Tim Fritzmann

Michiel Van Beirendonck

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Multiplierless Design of Very Large Constant Multiplications in Cryptography.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

FlexiPair: An Automated Programmable Framework for Pairing Cryptosystems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Efficient Loop Abort Fault Attacks on Supersingular Isogeny based Key Exchange (SIKE).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2020

A Framework to Counter Statistical Ineffective Fault Analysis of Block Ciphers Using Domain Transformation and Error Correction.

[BibT_eX]

[DOI]

IEEE Trans. Inf. Forensics Secur., 2020

Neural Network-based Inherently Fault-tolerant Hardware Cryptographic Primitives without Explicit Redundancy Checks.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

A Minimalistic Perspective on Koblitz Curve Scalar Multiplication for FPGA Platforms.

[BibT_eX]

[DOI]

Siddhartha Chowdhury

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Cryptographically Secure Multi-tenant Provisioning of FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2020

Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based Microcontrollers.

[BibT_eX]

[DOI]

Tim Fritzmann

Georg Sigl

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Fault Template Attacks on Block Ciphers Exploiting Fault Propagation.

[BibT_eX]

[DOI]

Proceedings of the Advances in Cryptology - EUROCRYPT 2020, 2020

2019

High-Speed Implementation of ECC Scalar Multiplication in GF(p) for Generic Montgomery Curves.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Combining PUF with RLUTs: A Two-party Pay-per-device IP Licensing Scheme on FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2019

CC Meets FIPS: A Hybrid Test Methodology for First Order Side Channel Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Lightweight Design-for-Security Strategies for Combined Countermeasures Against Side Channel and Fault Analysis in IoT Applications.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2019

Automatic generation of HCCA-resistant scalar multiplication algorithm by proper sequencing of field multiplier operands.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2019

Breach the Gate: Exploiting Observability for Fault Template Attacks on Block Ciphers.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Post Quantum ECC on FPGA Platform.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2019

Count Your Toggles: a New Leakage Model for Pre-Silicon Power Analysis of Crypto Designs.

[BibT_eX]

[DOI]

J. Electron. Test., 2019

Enhancing Fault Tolerance of Neural Networks for Security-Critical Applications.

[BibT_eX]

[DOI]

CoRR, 2019

Revisiting the Security of LPN Based RFID Authentication Protocol and Potential Exploits in Hardware Implementations.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019

Number "Not Used" Once - Practical Fault Attack on pqm4 Implementations of NIST Candidates.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2019

2018

The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2018

Customized Instructions for Protection Against Memory Integrity Attacks.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2018

Minimalistic Perspective to Public Key Implementations on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Revisiting FPGA Implementation of Montgomery Multiplier in Redundant Number System for Efficient ECC Application in GF(p).

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Two Efficient Fault-Based Attacks on CLOC and SILC.

[BibT_eX]

[DOI]

J. Hardw. Syst. Secur., 2017

Opening pandora's box: Implication of RLUT on secure FPGA applications and IP security.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Side Channel Evaluation of PUF-Based Pseudorandom Permutation.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Conference on Digital System Design, 2017

Using Tweaks To Design Fault Resistant Ciphers (Full Version).

[BibT_eX]

[DOI]

Sikhar Patranabis

Proceedings of the Computing Frontiers Conference, 2017

2016

Side-Channel Watchdog: Run-Time Evaluation of Side-Channel Vulnerability in FPGA-Based Crypto-systems.

[BibT_eX]

[DOI]

Souvik Sonar

IACR Cryptol. ePrint Arch., 2016

What Lies Ahead: Extending TVLA Testing Methodology Towards Success Rate.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Exploiting Safe Error based Leakage of RFID Authentication Protocol using Hardware Trojan Horse.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2016

Fault Based Almost Universal Forgeries on CLOC and SILC.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2016

Secure public key hardware for IoT applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

SmashClean: A hardware level mitigation to stack smashing attacks in OpenRISC.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016

Accelerating OpenSSL's ECC with low cost reconfigurable hardware.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Integrated Circuits, 2016

Shuffling across rounds: A lightweight strategy to counter side-channel attacks.

[BibT_eX]

[DOI]

Sikhar Patranabis

Praveen Kumar Vadnala

Santosh Ghosh

Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Parsimonious design strategy for linear layers with high diffusion in block ciphers.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

Inner collisions in ECC: Vulnerabilities of complete addition formulas for NIST curves.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

Improved Atomicity to Prevent HCCA on NIST Curves.

[BibT_eX]

[DOI]

Proceedings of the 3rd ACM International Workshop on ASIA Public-Key Cryptography, 2016

2015

Reconfigurable LUT: Boon or Bane for Secure Applications.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

ECC on Your Fingertips: A Single Instruction Approach for Lightweight ECC Design in GF (p).

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Using Tweaks To Design Fault Resistant Ciphers.

[BibT_eX]

[DOI]

Sikhar Patranabis

IACR Cryptol. ePrint Arch., 2015

Exploiting the Order of Multiplier Operands: A Low Cost Approach for HCCA Resistance.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2015

Reconfigurable LUT: A Double Edged Sword for Security-Critical Applications.

[BibT_eX]

[DOI]

Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2015

From theory to practice of private circuit: A cautionary note.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Integrated Sensor: A Backdoor for Hardware Trojan Insertions?

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

Tile Before Multiplication: An Efficient Strategy to Optimize DSP Multiplier for Accelerating Prime Field ECC for NIST Curves.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Role of power grid in side channel attack and power-grid-aware secure design.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs.

[BibT_eX]

[DOI]